Skip Navigation.
Section 0

Hardware Description and Specifications

This is an excerpt (Appendix O) from the Sequencer Manual related to the Apple II interface card. The entire manual may be added to the site at some point in the future, but for now this is probably the most useful and interesting information from it.

A Schematic and component layout drawing of the Interface PC board is included in this section for your reference. It is included solely for the purposes of explanation and is not to be used for servicing your own board. Refer servicing to an authorized Fender Service Center or call the Fender Service Department.

Chroma/Computer Interface PC Board Schematic

Chroma/Computer Interface Component Layout

The Interface PC Card

The hardware of the Interface PC Board is divided into the following sections:

  1. I/O Address Decoder
  2. Chroma Port
  3. Expander Port
  4. Interrupt Control
  5. Click output
  6. Clock Circuit
  7. Analog to Digital Converter
  8. Status Input Port

Interconnection is provided by:

I/O Address Decoder

The address decoder circuitry uses the DEVICE select, R/W, Phase 1 clock and three least significant address lines to decode the addresses of the various I/O functions on the Interface Card. The software locations of these functions are detailed in APPENDIX J and will not be repeated here. The outputs of Z10 and Z15 are active low enable pulses that are used to latch data and/or enable the reading or data from tri-state buffers. They are also used to provide control pulses ror clearing the interrupt, starting the ADC, selecting the timer source and outputting a click track pulse.

The Chroma port consists of an 8-bit input port with handshaking and an 8-bit output port with handshaking. The port connects to a mirror image of itself in the Chroma; that is, each input port line (mnemonics starting with XI) connect to the corresponding output port line (mnemonics starting with XO) at the other end of the interface. The interface really only consists of the output latch (Z5), the input tri-state driver (Z7), the four NAND gates and an inverter. The two transistors Q3 and Q4 are for isolation when the power is shut off. All the other stuff is just for noise rejection. When the Sequencer wants to transmit a byte of data, it checks the XOFULL line by reading the Status Input Port to see if the last byte it sent has been received yet. When it has, it writes the byte into the latch with the WREXTO strobe coming from the I/O Address Decoder. This causes the flip-flop consisting of gates Z11a and Z11b to be set, and pulls the XOFULL line low. This tells the Sequencer that the output port is full (and not to send any more data yet) and tells the other end of the interface that there is fresh data to be had. When the other end reads the data, it will pulse the acknowledge line XOACK, which resets the flip-flop and resets ZOFULL high (inactive) again. This tells the Sequencer that it can send another byte of data.

The input interface performs the other side of the same task. When data arrives from the other end via the XI lines, the XIFULL line will go low, telling the Sequencer that the fresh data has arrived. When it reads it, using the RDEXTI strobe, the acknowledge XIACK will be pulsed, causing the flip-flop at the other end to be cleared, and causing XIFULL to go high (inactive) again.

The remaining gates Z11d and Z11c are used to allow masking of the XOFULL and XIFULL lines for interrupt control.

Interrupt Control

Normally, the Sequencer is ready to accept data from the interface, and the XIMASK line from Z16b is high (inactive). This means that an incoming byte, which is accompanied by XIFULL going low, will cause the input of Z12c to go low, turning on Q1 and interrupting the Apple. The only times the Sequencer activates XIMASK to prevent input interrupts is if the device at the other end of the interface is sending data faster than the Sequencer can process it.

Normally, the Sequencer has no data to transmit, and if it does, the interface is usually ready for it, as signified by a high (inactive) XOFULL. Tf, however, the Sequencer has data to send and the output port is stil full from the previous data transfer, the Sequencer will store the byte of data in a FIFO (first in first out) queue in its memory and set XOMASK high (inactive) from Z16a, thus unmasking output port interrupts. The output port interrupt occurs whenever the device at the other end of the interface gets around to reading the data off the interface and sending back an XOACK pulse. Then the Sequencer will take time out from whatever it is doing to pull a byte from the end of the FIFO queue and output it. Only when the queue is empty does the main computer mask output interrupts again by setting XOMASK low (active).

Upon power-up, the XOMASK is set low (active) and XIMASK is set high (inactive) by the system RESET line. Interrupts can also occur from the Clock Circuit. Interrupts from the Clock Circuit cannot be masked, see APPENDIX N.

The Sequencer determines the source or the interrupt by reading the XOFULL, XIFULL and TIME lines from the Status Input Port.

Expander Port

The Expander Port works exactly like the Chroma Port except it is polled instead of interrupt driven. The Sequencer determines the state of the port by reading the XXFULL and IXFULL lines from the Status Input Port.

Status Inout Port

The Status Input Port consists of two tri-state drivers that buffer the state lines of the interrupt sources as described above. It also allows the Sequencer to read the state of the FOOTSWITCH, SYNC and Analog to Digital Converter. The RC network of R19/20 and C42 provide some debouncing of the FOOTSWITCH.

Click Output

The Click output consists of Z17b, R36 pullup and bandpass filter R16/C35/R17. A 100pF capacitor at the Click Out Jack completes the filtering. Everytime the click address is accessed via the I/O Address Decoder, the output of Z17b toggles, generating a pulse at the Click Out Jack. Emphasis is placed on the first beat of the measure by outputting two pulses, 42 microseconds apart, for subsequent beats of the measure. Two pulses this close together reduce the low frequency energy and the pulse sounds lower in volume.

The Clock for the Sequencer can be either an internal clock of 1000 Hz or an external clock of any frequency between DC and 3000 Hz. The lower the frequency, the less recording/playing resolution available. Ideal input frequency is 1000 Hz whereas 24 Hz is barely acceptable and frequencies above 3000 Hz will keep the Sequencer in constant interrupt service. For more information about the external clock frequency, see Chapter 10.

The flip/flop consisting of Z1c and Z1d allows switching between internal and external clocks by addressing the location decoded by the I/O Address Decoder.

The internal clock on 1000 Hz is generated by dividing the IM Hz system clock by 1024 in Z19. The internal clock is disabled by pulling the reset line high, forcing the Q10 output to remain low.

The external clock circuitry consists of Z18b comparator circuit and associated components. This circuit senses when the input voltage crosses zero plus a .05V hysteresis level, at which time the output of Z18b saturates at the negative supply level. When the input falls below -.05V then Z18b switches back to the positive supply level. The circuit is enabled by a low level at the output of Z1c and creates an input voltage divider R47 and R42. When Z1c is high, the input of Z18b will always be high enough to keep it from switching and the output will be negative.

The output of Z18b is rectified, divided and filtered so that it is compatible with the clock input of Z17a (0V to 5V), which generates the interrupt. R48 is necessary to offset the effect of the nonsymmetrical load of Z18b. The interrupt is cleared by a pulse from the I/O Address Decoder when the Sequencer has determined, be reading the Status Input Port, that the interrupt came from the timer.

Analog to Digital Converter

The ADC circuit is centered around the National 0804 single channel IC. The circuit converts the resistance of a 100K linear potentiometer in the pedal housing to a digital value between 0 and 255.

The reference of the ADC is set by R25. This effectively adjusts the range of digital values obtained. The minus input for the ADC is set by R29. Adjustment of this trimmer sets the zero value with the pedal all the way up. The Z18a circuit converts the pedal resistance to a voltage source with low impedance, which is sent to the ADC for conversion.

Conversion occurs within 100 microseconds and the INTR line goes low, telling the Sequencer that a conversion is finished. When the Sequencer reads the ADC value, the RD line goes low and the digital data is sent to the Apple via the Z8 buffer. The ADC conversion process is started again by pulling the WR line low on the 0804, which is done by the pulse from the I/O Address Decoder after the Sequencer reads the value.

It is possible to open circuit R33 and feed a 0-5V control voltage in the pedal input if you desire. Performing the modification will void your warranty unless performed by an authorized Rhodes Chroma Service Center.

ADC Adjustment Procedure

To adjust the ADC zero point and range, it is necessary to continuously view the value of the control pedal. You can do this by running USER UTILITY BANK 2, NUMBER 1 (ADC TEST) or USER UTILITY BANK 2, NUMBER 0 (the preferred Interface Test Program). Number 1 displays the value in decimal from 0 to 255 and NUMBER 0 will display the pedal value in HEX from 00 to FF when the k command is issued (see APPENDIX L).

Once the Sequencer is continuously displaying, push the pedal all the way in the up position and adjust trimpot R29 (the one closest to the rear of the APPLE) for 00 display. You should first adjust R29 until you start seeing 01's then back off until it is always 00. Then push the pedal all the way down and adjust trimpot R25 (the one closest to you) for FF (or 255 decimal) display. You should adjust from FE until the display always reads FF. Then push the pedal all the way up again and readjust for 00. Exit the ADC Test mode by typing a <RET> and exit the Interface Test Program by typing ^E.

Sync, External Clock, and Click Signal Specifications

SYNC Input

LEVEL: 0V to 5V, TTL (external device must be able to sink .9 mA @ .8V max, can use open collector because input is pulled up by 10K).

SPEED: Ton (min) = Toff (min) = 52 microseconds in SYNC CHECK mode (1.5 milliseconds in Single Step2 mode).

NOTE: If a footswitch is used for this input, it should be debounced unless sync delay is set to zero. Both single step timer sources debounce this input in software.


LEVEL: .7Vp-p minimum, 22Vp-p maximum.

INPUT IMPEDANCE: approximately 100K ohms.

WAVEFORM: Sine or Square (duty cycle 25% to 75%).

MINIMUM FREQUENCY: 0 Hz (although for useable resolution, a minimum of 100Hz is recommended).

MAXIMUM FREQUENCY: depends on complexity of sequence but generally should be limited to 3000 Hz.

Click Output

OUTPUT LEVEL: -2V to +2V nominal.