Polaris Service Manual: Circuit Descriptions
The Polaris Main Board includes the bulk of the circuitry in the Polaris, including the computer and synthesizer circuits. The sections of this board will be described pretty much in the order in which they appear on the schematics.
The Polaris' computer is Z1, an Intel 80186. This is a fast 16- bit microprocessor which includes a number of useful peripheral functions on the same chip, where the service technician doesn't have to worry about them. The main timing source is crystal Y1, which is connected to the oscillator pins on the computer and must be twice the desired system clock frequency, either 12MHz or 16MHz depending upon the speed 80186 used. The 80186-6 uses a 6MHz clock and must be used with a 12MHz crystal; initially, production units are being built this way. The 80186-3 uses an 8MHz clock and should be used with a 16MHz crystal; eventually, production units may be shipped this way, if the -3 version of the computer comes down in price.
The computer communicates with external devices, including its memory, over a 16-bit wide multiplexed address/data bus. This bus comes off the computer on pins AD0 through AD15. The 16 lsbs (least significant bits) of the address appear on these pins at certain times, and data appears on these pins at other times.
Data can flow over the bus one word (16 bits) at a time, in which case the entire bus is used, or one byte (8 bits) at a time, in which case one half of the bus (either the upper or lower) is used. A line called BHE/ (bus high enable) works with address bit 0 to indicate which halves of the bus are used:
|1||0||even-addressed byte on low half of bus|
|0||1||odd-addressed byte on high half of bus|
|0||0||even-addressed word on both halves of bus|
(Odd addressed words are accessed one byte at a time in two operations.) Note that address bit 0 could have been called BLE/ (bus low enable), as its function is perfectly symmetrical with the function of BHE/.
The computer communicates with external devices by "running bus cycles". A bus cycle is a sequence of events that causes an external device to be selected and causes data to be transferred. A bus cycle goes like this:
The computer indicates the direction of the transfer using the DT/R/ (data transmit/receive) line. This line is intended for controlling the direction or external bus transceivers such as Z17.
The computer identifies the device it wishes to communicate with by putting out an address. This involves the following:
The ALE (address latch enable) signal is raised. This causes latches Z14 and Z15 to "open up", so that the signals on their inputs will appear at their outputs.
The computer places the 16 lsbs of the address on pins AD0 through AD15. The 4 msbs of the address appear on four other pins that aren't used, so they aren't shown in the schematic. BHE/ is also driven.
The computer internally decodes the msbs of the address into a number of chip select signals. These include I/O device chip selects PCS0/ through PCS6/, RAM chip selects MCS0/ through MCS3/, and EPROM chip select UCS/. One of these is activated. An additional chip select, LCS/, is not used, and so is not shown in the schematic.
ALE is lowered, latching the 16 lsbs of the address. These bits remain stable at the outputs of Z14 and Z15 for the rest of the cycle.
Since the address has now been latched, the address is removed from lines AD0 through AD15.
If the operation is a memory write or an output, data is placed on the AD0 through AD7 lines, and/or the AD8 through AD15 lines.
Either the RD/ (read strobe) or WR/ (write strobe) line is activated, depending upon the direction of the transfer. This strobe initiates the data transfer. At about the same time, DEN/ (data enable) goes active. This signal is intended to enable external bus transceivers such as Z17.
If the operation is a memory read or an input, the selected device puts its data on the AD0 through AD7 lines, and/or the AD8 through AD15 lines.
After a certain amount or time the read or write strobe pulse is terminated. Normally, the width of this pulse is two clocks (333ns at 6MHz, 250ns at 8MHz), but certain I/O accesses take extra clocks. DEN/ is also deactivated.
The device driving the data bus (either the computer, the memory, or an input device) turns off its bus drivers.
At this point, the bus is ready for another bus cycle. Frequently, another cycle follows immediately at a maximum rate of one cycle every four clocks. If the computer does not need to access memory or an I/O device immediately, though, one or more idle clocks will be inserted between bus cycles.
The computer accepts two external signals from the power supply. DC OK connects (through two inverters) to the RES/ input to the computer. When the +5V supply is out or regulation, this line holds the computer in a reset state. AC OK connects (through an inverter) to the NMI/ input to the computer. When AC OK goes low, indicating that the power switch has been turned off, this generates a "non-maskable interrupt" to the computer. This causes the computer to drop whatever it is doing and execute a special program that mutes the master volume VCA and then halts.
The computer accepts a number of other signals from other devices on the Main Board via the 4x4 jumper platform. A high-level signal on one of the interrupt inputs INT0 through INT3 causes the computer to temporarily drop whatever it is doing and execute a short program to service the device that generated the interrupt signal. Normally, the interrupt program performs an input or output operation that cancels the interrupt request. If a hardware problem prevents the interrupt request from being cancelled, the computer will get interrupted over and over again.
A high-level signal on one of the DMA request inputs DRQ0 or DRQ1 causes the on-chip DMA controller to interleave two bus cycles between the cycles used by the computer. If the DMA controller is inputting data, the first cycle will be an input and the second cycle will be a memory write. If the DMA controller is outputting data, the first cycle will be an output and the second cycle will be a memory read. The input or output cycle normally clears the source of the DMA request.
A few miscellaneous gates are also associated with the computer. Z19A, Z20A and Z20D split chip select UCS/ into two chip selects, UCS0/ and UCS1/, depending upon the state of an address bit. The particular address bit used for this purpose is jumper-selectable, depending upon the size of EPROM installed for Z12 and Z13. Z21A through D split the read and write strobes into two pairs of strobes, one pair for each half of the data bus. RD/ and WR/ are gated with A0 to generate RD LO/ and WR LO/, which are the strobes for all devices on the lower half of the data bus; including all even-addressed memory. RD/ and WR/ are also gated with BHE/ to generate equivalent strobes for the upper half of the data bus, which contains only odd-addressed memory.
The memory consists of up to six pairs of byte-wide memory chips. Since the chips are 8 bits wide and the data bus is 16 bits wide, memory chips are always used in pairs. Sockets Z2 through Z9 are used for CMOS RAM, and are provided with read and write strobes, battery backed up power, and isolation transistors on the chip selects. Sockets Z10 through Z13 are used for EPROM and are provided with read strobes only, no battery backup, and no isolation transistors on the chip selects.The system supports two types of RAM chips, 6116s, which are 2Kbyte chips, and 6264s, which are 8Kbyte chips. When the larger chips are used, the write strobes go to pin 27 on the chips and the two jumpers between the rows of chips connect address bit 12 to pin 21. When the smaller chips are used, they are installed such that socket pins 1, 2, 27 and 28 are empty. The two jumpers steer the write strobes to socket pin 21 (which is chip pin 23). Five configurations are allowed:
|total size||chip size||chip type||chip count||where installed|
|16K||2K||6116||8||Z2, Z3, Z4, Z5, Z6, Z7, Z8, Z9|
|32K||8K||6264||4||Z2, Z3, Z4, Z5|
|48K||8K||6264||6||Z2, Z3, Z4, Z5, Z6, Z7|
|64K||8K||6264||8||Z2, Z3, Z4, Z5, Z6, Z7, Z8, Z9|
As long as the jumpers are positioned according to the size of the chips, the software can determine how much memory is present in the system.
The isolation transistors on the chip selects to the CMOS RAMS are cascode transistors whose bases are powered from the DC OK signal. During normal operation these act as saturated switches that pass the chip select signals to the RAM chips. When DC OK is inactive, though, the chip select signals don't reach the RAM chips. For instance, when the power is off the emitters and bases of these transistors are all at 0V, so the transistors are off; the collectors are pulled up to the battery backup power supply by the pullup resistors.
The system supports two types or EPROM chips, 2764s, which are 8Kbyte chips, and 27128s, which are l6Kbyte chips. The jumper by Z19A, located near the left rear corner of the board, determines the number of addresses occupied by each pair of chips. Four configurations are allowed:
|total size||chip size||chip type||chip count||where installed|
|32K||8K||2764||4||Z10, Z11, Z12, Z13|
|64K||16K||27128||4||Z10, Z11, Z12, Z13|
Memory chips must be changed with the power off, obviously. CMOS RAM chips, though, must also be changed with the battery disconnected. You should unplug J15 from the main board before changing any CMOS RAM chips; it is not sufficient to remove a battery from the holder, as the capacitor on the holder retains its charge for a minute or more.
Note also that if you change EPROMS to a different software revision, the memory locations used for different purposes usually change, so all software adjustments will probably need to be redone and the programs and sequences reloaded. As a matter of courtesy to your customers, you should always save all programs and sequences on cassette before working on the instrument and reload them when you are finished.
When the DC OK signal is active, indicating that the +5V digital supply is within regulation, Q5 is turned on. This turns on Q6, connecting the +5V BAT rail to the +5V digital supply. Capacitor C1 limits the rate at which the power can switch. Since the battery voltage is only about +3V, CR1 will be reversed biased.
When the DC OK signal is inactive, Q5 and Q6 are off and the +5V BAT rail is connected to the battery through CR1. This diode is a germanium diode because of its low forward voltage drop. When the power is off, transistor Q6 is in an unusual state: its collector is more positive than its emitter. A transistor, though, can be operated upside-down. When it is, its emitter acts as a collector and its collector acts as an emitter. R12 connects the base to the "emitter" holding the upside-down transistor off.
The data bus is split into two buses, the "data in/out bus" (lines DI0 through DI7) and the "data out bus" (lines DO0 through DO7). The data out bus is driven by bus driver Z16 whenever the computer is writing or outputting; it connects to all output devices that present a significant load to the bus. The data in/out bus is connected directly to the computer and goes to all input devices and all bidirectional devices, including the even addressed memory chips. (It also goes to one output device.) Thus, devices like memories, which don't have very strong bus drivers, don't have to drive a heavily loaded bus.
J10 provides a data bus and control signals to the control panel. In the Polaris it is a 26-pin connector, although the board is laid out to accept a 34- or 40-pin connector, in case more lines are needed in another application. The data bus to the control panel is a bidirectional bus, isolated by transceiver Z17. This chip is only enabled when PCS3/ is active, indicating that a device on the control panel is being addressed. Bus driver Z18, which is also enabled by PCS3/, places address bits 1 through 6 onto lines A0 through A5 and places the RD LO/ and WR LO/ strobes onto the RD/ and WR/ lines to the panel. The STB (signal is an active-high OR of the two strobes, the SEL/ signal is a buffered PCS3/, and the R/W/ (read/write) is a version of DT/R/ gated with PCS3/.
J10 also carries a DC OK signal, power (including battery power), and some analog signals.
Sheet two of the schematic includes some miscellaneous decoding and and I/O chips.
Z29 is an 8-to-1 multiplexer that acts as eight single-bit input ports. When PCS1/ is active, a RD LO/ strobe will cause one of the eight inputs to this chip to be placed on data bus bit DI0. The particular input selected depends upon address bits A1, A2 and A3. Input 0 is the end or conversion signal from the analog to digital converter. Inputs 1 and 2 are the two footswitch inputs. Input 3 comes from the timer interface circuit. Input 4 is a status signal from the MIDI/Triad interface. Inputs 5 and 6 are not used. Input 1 comes from a jumper that is used to tell the software whether the system is running at 6MHz or 8MHz.
Z30 is an 8-bit addressable latch that acts as eight single-bit output ports. When PCS1/ is active, a WR LO/ strobe will cause the bit on DO0 to be written to one of the eight outputs of this chip. The particular output selected depends upon address bits A1, A2 and A3. Output 0 controls the cassette motor control relay. Output 1 is not used in the Polaris. Output 2 ultimately controls the serial output data to the cassette or sync output. Output 3 selects the cassette and sync output level. Outputs 4 and 5 enable the sample and hold circuits. Outputs 6 and 7 switch the cassette input and output into or out of the audio output.
Z28 is a dual 4-bit strobe decoder. When PCS0/ is active, a RD LO/ strobe will be steered to one of four places, depending upon address bits A1 and A2. Except for the RD ADC/ output, these strobes are not actually used to read data into the computer. Instead they are used only to set or clear flip-flops, and the garbage read in on the bus is ignored. When PCS0/ is active, a WR LO/ strobe will be steered to one of four different places, depending upon the same address bits. The START ADC/ output is not actually used to write anything, so the data written is ignored.
Z27 is an 8-bit strobe decoder. When either RD LO/ or WR LO/ occurs, pin 6 will go high. If PCS4/ is active, one of the eight outputs will generate a strobe pulse, depending upon address bits A1, A2 and A3. Some of these are write strobes and some are read strobes, but there is no confusion because the software never attempts to input from an output location or output to an input location. The WR RXDIS/ and We RXEN/ lines are not actually used to write anything. Instead they are used to clear and set a flip-flop, so the data written is ignored.
Outputs 6 and 7 from Z27 are not directly connected. Instead, the I/O locations represented by these strobes are decoded by Z85D. If address bits A2 and A3 are both high, indicating that output 6 or 7 is selected, the MIDI interface UART, Z87, is selected, and A1 selects one or two registers inside that chip.
The footswitches are momentary switches to ground, either normally open or closed. (Their state is sensed on power-up.) The RC network on these inputs filters the switch bounce and the Schmitt trigger inputs of Z46C and D square up the signal again. This eliminates the need for software debouncing.
When PCS2/ is active, a WR LO/ strobe will cause the four bits on data bus lines DO0 through DO1 to be latched by Z33. This four bit number is decoded by Z35 and Z36 into 16 lines, KS0A to KS7B, one of which will be activated at any one time. Each line selects a bank of eight keyswitches; the state of the selected bank appears on KD0 through KD7. If a particular switch is open, the corresponding ID line will be pulled high by its pullup resistor. If a particular switch is closed, the corresponding KD line will be pulled low through a diode on the keyboard itself. When PCS2/ is active, a RD LO/ strobe causes the state of the selected bank to be gated onto data bus lines DI0 through DI7.
When the MOTOR/ line from Z30-4 is low, relay K1 is energized. When the line is high, the relay is released. CR2 protects against inductive kick-back from the relay coil.
Z31 is another addressable latch. When PCS5/ is active, a WR LO/ strobe causes the bit on DO0 to be written into one of the eight outputs, depending upon address bits A1, A2 and A3. Six of these select whether each synthesizer channel routes its output to the main output of the autotune timer. The remaining two are used to generate pulses for the click circuits.
Z32 is an 8-bit strobe decoder. When PCS6/ is active, a WR LO/ strobe is steered to one or seven places, depending upon A1, A2, and A3. Six of these strobes go to latches in each synthesizer channel, allowing data to be written to each channel. The seventh strobe goes to a latch that holds the number of the currently selected sample and hold.
The Chroma Interface consists of two independent, symmetrical parallel ports, one for input and the other for output. When the WR CHROMA/ strobe (from Z27) happens, a byte or data is latched into Z22 and delivered to the CO0 to CO7 lines. The strobe also clocks a 1 into flip-flop Z26A, pulling down the CO FULL/ line. Transistor Q7 simply isolates this line when the power is shut off, just like the isolation transistors on the CMOS RAM chip select lines. This output is an open-collector and is pulled up by a resistor in the receiving device. Typically, this signal interrupts the device at the other end, which reads in the byte and generates a pulse on CO ACK/. This pulse clears flip-flop Z26A, causing CHROMA OUT REQ to go high. This interrupts the Polaris' computer so that it can output the next byte.
When a byte is received on the CI0 through CI7 lines from an external device, that device pulls CI FULL/ low. Z26B acts as an inverter, causing CHROMA IN REQ to go high. This interrupts the Polaris' computer so that it can read in the byte. When the RD CHROMA/ strobe (from Z27) happens, the byte is placed on data bus lines DI0 through DI7. The strobe is also sent out over the CI ACK/ line, which normally causes the device at the other end to negate the CI FULL/ line. It also normally interrupts the device at the other end so that it can transmit the next byte. The CI ACK/ line also has an isolation transistor so that it will not be held active when the power is shut off.
Z83 and associated gates act as a clock divider. The CLKOUT signal comes from the computer and is either 6MHz or 8MHz. This is divided by either 6 or 8, depending upon the jumper on Z83-9, to produce a 1MHZ clock on Z83-12. This is further divided to 500KHz on Z83-11. When the WR RATE/ strobe (from Z27) happens, the bit on DO0 is written into flip-flop Z25B and this determines which clock, the 1MHz or the 500KHz, gets through Z23B and C (open-collector NAND gates). The selected clock is applied to the RxC (receive clock) and TxC (transmit clock) inputs on Z87.
Z87 is a UART (universal asynchronous receiver/transmitter) that communicates information serially at a baud rate (number or bits per second) that is 1/16th of its clock rate. Thus, the baud rate is either 31.25K or 62.5K. This chip is outputted to or inputted from whenever PCS4/ is active and A2 and A3 are both 1. The chip is controlled by doing an output with A1 low and its status is sensed by doing an input with A1 low. A byte of data is given to the chip for transmitting by doing an output with A1 high and a received byte as inputted from the chip by doing an input with A1 high. The DR/T/ signal (the inversion of DT/R/) tells the chip whether an access is an input or an output.
Transmitted data comes from Z81D to output pin J11-6. This a current loop output whose return path is on J11-4. Received data comes in as a current in J11-1, through opto-isolator Z86, and out J11-3. The output of the opto-isolator goes to the RxD (receive data) pin on the UART.
Flip-flop Z47B and open-collector NAND gates Z23A and Z23D allow the output to be driven by either the TxD (transmit data) pin on the UART or by a copy of the received data. The first mode is called OUT mode and the second is called THRU mode. Generating a WR THRU/ strobe (from R27) causes Z47B to be set, putting the output in THRU mode. Activating the RTS/ output from the UART forces the output into OUT mode. The RTS/ output is a general purpose bit controlled by writing to the UART's control register.
Flip-flop 247A controls the DCD/ (data carrier detect) input to the UART. When low, the UART receiver is enabled. When high, the UART receiver is held reset. This flip-flop is manipulated by generating WR RXDYS/ and WR RXEN/ strobes (from Z27). In the Polaris it is left set, so that the receiver will be enabled.
When a byte of data is received, the IRQ/ output from the UART goes low. This is an open-drain output pulled up by R95. When this goes low, U REQ (UART request) goes high. This is jumpered into the DRQ0 input to the computer. The computer's DMA controller reads in the byte from the UART's data register, causing IRQ/ to go high and U REQ to go low again until the next byte is received.
When a byte of data is to be transmitted, the computer writes it to the UART data register. No interrupt or DMA request is needed to tell the computer that the UART is ready for output. Instead, the computer checks the status of the UART to see if it can accept a byte of data whenever the computer is interrupted by its timer. The timer interrupt occurs at 2400Hz, so the status is checked plenty often enough.
Counter Z84 and sections or Z82, Z85, and Z47 are not used in the Polaris. The purpose of these circuits is to support a proprietary interface protocol under development at Fender.
Timer 1 inside the computer is used to measure the period of a number of input frequencies. The WR TSEL/ strobe (from Z28B) causes a four-bit number to be written into latch Z39. If the msb of this number is 0, data selector Z38 will be enabled, and the other three bits will select one of the inputs to appear at Z73-5 and Z42-6. If the msb or this number is 1, Z38 is turned off and switch Z48D is turned on, causing the state of the SERIAL IN line, buffered and inverted by Z46B, to appear at the same point. Input 0 on data selector Z38 comes from the SYNTH ZCD line, buffered by Z46A, and the remaining 7 inputs come from successive outputs of a binary counter driven by the same signal. Thus, depending upon the number in latch Z39, any of nine signals can appear at Z73-5 and Z42-6:
- 0000 — SYNTH ZCD
- 0001 — SYNTH ZCD / 2
- 0010 — SYNTH ZCD / 4
- 0011 — SYNTH ZCD / 8
- 0100 — SYNTH ZCD / 16
- 0101 — STNTH ZCD / 32
- 0110 — SYNTH ZCD / 64
- 0111 — SYNTH ZCD / 128
- 1000 — SERIAL IN
The first eight are used during autotune, so that the period of a signal can be accumulated over multiple cycles if the frequency is high. The last is used during cassette operations and for sync input.
The input thresholds of Z46A are normally 1V and 2V. R21 injects current into an internal node that shifts these thresholds so that they are roughly centered around ground. The SYNTH ZCD signal is a high-level analog signal that comes back from the synthesizer voice being tuned, so Z46A acts as a Schmitt trigger zero-crossing detector. The capacitor simply makes the chip less sensitive to noise pickup.
Z46B works the same way, although the resistor connected to its internal node can be switched in and out by Z48A, under control of the SER LEVEL line (from Z30). Thus, the input threshold can be adapted for use with audio signals centered around 0V or digital signals centered around 1.5V.
Whatever input signal is selected is fed into Z73C and Z42B, C and D. These gates act as an exclusive-or gate, selecting either the input signal or its inversion depending upon the state of flip-flop Z43A. Whichever polarity is selected is fed into the clock input of Z43B, so that when a positive edge occurs, Z43B will be set. When this flip-flop is set, three things happen:
- The T REQ (timer request) line goes high, interrupting the computer.
- The T GATE (timer gate) line goes low, stopping Timer 1 inside the computer so that the computer can read it.
- Z43A is toggled, causing the opposite polarity of the input signal to be routed into Z43B.
Once the computer has read and reset Timer 1, it generates a CLR T REQ/ strobe (from Z28A). This does three things:
- The T REQ line goes low, removing the interrupt request.
- The T GATE line goes high, allowing Timer 1 to run.
- Z43B is made ready to detect another edge.
Thus, this circuit can measure the time between zero-crossings or any signal. This can be used to measure pulse width or frequency of a synthesizer signal or receive information from a cassette.
When the SERIAL IN line is being used as a sync input, the circuit is used somewhat differently. Since sync pulses are much slower, only the occurrence of the interrupts are monitored and the actual period measurements are discarded. Since only one polarity of sync input is important, the computer arbitrarily sets or resets Z43A after each sync pulse, so that only the desired polarity edge will be looked for. The computer does this by generating SET POL/ or CLR POL/ strobes (from Z28A).
The cassette and sync systems also require output. All output is quantized to a 2400Hz clock, appearing on the SER OUT CLK line. The pulses on this line coincide with timer interrupts inside the computer. The timer interrupt program calculates the correct state of the serial output and puts the bit onto the SER OUT line (from Z30). The next SER 0UT CLK clocks this into Z52A, cleaning up the timing. The output of Z52A is attenuated to a low level audio signal and fed into opamp buffer Z40. If the SER LEVEL signal is low, switch Z48C will be off and the op-amp will function as a simple voltage follower, so the SERIAL OUT line will have a low-level audio signal on it. If the SER LEVEL signal is high, switch Z48C shorts the negative input to the opamp to ground, causing it to function as a comparator. The low-level signal is thus converted to a very high-level signal that is roughly RS-232C compatible.
The SERIAL IN and SERIAL OUT lines can be mixed into the audio output via the DATA AUD line. This line is a separate audio path to the Output Board and is used for all signals other than the synthesizer outputs. If the SER OUT MUTE line (from Z30) is low, the serial output data will pass through Z42A, Z73F and Z73D, and get mixed into the DATA AUD line. If the SER IN MUTE/ line (also from Z30) is high, the serial input audio signal will pass through Z48B and get mixed into the DATA AUD line. CR3 and CR13 protect the CMOS switch from excessive input levels.
The metronome click is generated by raising HI CLICK (from Z31) for a few microseconds and then lowering it again. The duration of the pulse is controlled by the software and determines the ultimate volume of the click. This pulse injects a transient into hi-Q bandpass filter Z41A, giving the click a pleasing pitch.
The switch press click and error burp sounds are generated in the same manner by the LO CLICK signal. Bandpass filter Z41B is tuned to a lower frequency. The burp sound is simply a number of clicks in rapid succession.
The analog ground and +5V supplies connect to the ADC GND and ADC REF lines at the A/D converter circuit, thus providing a common reference for the A/D and all analog inputs. The A/D chip expects an analog input in the range of 0V to two times its reference voltage, so the reference is divided down to +2.5V with trimmer R45.
The A/D chip is a self-clocked device that has its own on-chip RC oscillator, using the CK0 and CK1 pins. A conversion is performed by presenting a stable analog input, generating a WR/ strobe (from START ADC/, from Z28B), and waiting for the INTR/ output (to EOC/, to Z29) to go low, which takes about 100 or 200 microseconds. When it goes low, the converted number can be read by applying a RD/ strobe (from RD ADC/, from Z28A). In the Polaris the conversions are initiated by the timer interrupt program at a fixed 2400Hz rate. Every tick of the timer the interrupt program checks EOC/, reads in the completed conversion using RD ADC/, selects a new analog input by writing a byte to a device on the control panel, and starts the new conversion by strobing START ADC/.
This circuit is a l4-bit precision multiplying D/A converter with bipolar output. The nominal output range is roughly -5V to +5V when presented with a +3V reference input. The 14-bit number is output to the D/A converter in two operations. The LSB is written using the WR DAC L/ strobe and the MSB is written using the WR DAC H/ strobe (both from Z28B). Trimmer R46 is used to adjust the offset voltage of Z58 so that it is within 200uV or 0V, necessary to maintain the accuracy of the D/A converter chip.
Each sample and hold circuit in the synthesizer channels is assigned a six-bit number. The 3 msbs identify one of the six channels and the 3 lsbs identify one of the six sample and holds within that channel. Actually, one channel has a seventh sample and hold used for master volume. A sample and hold is selected by writing a number into latch Z63 using the WR SH SEL/ strobe (from Z32). The three lsbs go in parallel to all six synthesizer channels, but the three msbs are decoded by Z60 and Z61 into individual strobes for each channel. When the SH DISABLE line (from Z30) goes low, the selected output of Z61, one of the lines SLOW0/ through SLOW5/, will go low. In addition, if the SH LAG line is low at the same time, the selected output of Z60, one of the lines FAST0/ through FAST5/, will go low.
Z62 is a multiplexer that selects the reference input to the D/A converter. When one of the oscillator pitch or filter cutoff sample and holds is selected, the SHA0 line will be low, so diodes CR8 and CR9 will be turned off. In this state the temperature compensation line from the selected synthesizer channel, which is nominally at around +2.5V, is used as the D/A converter reference. If any other sample and hold is selected, SHA0 will be high, causing either Z62-2 or Z62-4 to be selected, providing a fixed +3V reference to the D/A converter.
This circuit is a digital noise generator that generates a pseudo-random sequence of bits at about 100KHz that repeats about every 1.3 seconds. This bit stream sounds like white noise and is filtered into something more like pink noise and buffered.
Z49 is a bus driver that isolates the data bus that goes to the synthesizer voice from the main data bus, for noise considerations. It is enabled whenever PCS6/ is active and address bits 2 and 3 are not both 1. In other words, it is active whenever Z32 is generating one of the strobes WR SYN 1/ through WR SYN 6/.
Sheet four of the schematic details a single synthesizer voice. This circuit is repeated six times.
The DAC line from the D/A converter contains all the control voltages for all channels, time-multiplexed. This goes to ZX01 and ZX02 in each voice. These are the sample and hold switches. When the selected channel's SLOW(N)/ line goes low, the switch inside of ZX01 selected by SHA0 through SHA1 is turned on, connecting the DAC line to one of the 0.033uF capacitors. These capacitors connect through 1Mohm resistors to 0.0068uF capacitors at the input to the FET-input op-amp buffers in ZX03 and ZX04. This RC network causes changes in any particular control voltage to be smoothed out, rather than being sudden steps. The time constant of the RC networks is somewhere around 8ms.
If a sudden change in a control voltage is needed, the selected channel's FAST(N)/ line goes low at the same time as the SLOW(N)/ line. The DAC voltage is thus delivered equally to both capacitors and the smoothing effect is overridden.
Voice 5 has an additional sample and hold consisting of capacitor C12 and buffer Z503C, used for the master volume. In the other voices the input to ZX03C is shorted to ground.
ZX05A and B is a dual oscillator chip. Each half accepts a low-level pitch control voltage (scaled at roughly l8mv/octave) on pin 7 or 12, generates a triangle wave on the capacitor connected to pin 6 or 13, a buffered triangle wave on pin 5 or 14, and a buffered sawtooth on pin 2 or 17. Pins 8 and 11 are reference current inputs to the exponential converters inside the chip. Pins 4 and 15 are internal reference voltages that require external bypassing. Pins 1, 9 and 18 are supply pins. Pin 10 is the temperature compensating voltage generated by the chip; this voltage is nominally +2.5V, but is proportional to the temperature of the chip. Pin 16 is a sort sync input, which isn't used, and pin 3 is a hard sync input, which forces ZX05A to the beginning or a cycle whenever a negative pulse is applied. This pulse is derived by differentiating the sawtooth from the other side of the chip through a tiny capacitor (CX23). Switch ZX08B grounds this signal, preventing or allowing the sync.
The sawteeth are converted into pulses by comparators ZX06A and ZX06B. The pulse width is determined by a control voltage in the nominal range of -4V to +4V. The comparators have a bit of positive feedback to keep them from oscillating. The pulse outputs are mixed in with the pulse control voltage to yield a DC-free signal. If switch ZX07A or ZX08A is on, the sawtooth signal will be mixed in as well. ZX07C switches in the noise signal as well and ZX07B replaces the upper oscillator signal with the digital ring modulation of the pulses from the two oscillators. The ring modulator is made from one exclusive-or gate from either Z70 or Z71 (located in the area between channels 3 and 4).
The oscillator signals feed into signal processor ZX09 on pins 6 and 7. These inputs are low-level inputs, so the 510ohm resistors on these inputs attenuate the oscillator signals. Pins 5 and 8 adjust the levels of the signals; the A signal is always on, and the B signal is turned off when the ring mod is selected.
The signal processor includes a four-pole low-pass filter, using capacitors CX25 through CX2T. The filter is tuned by the CUTOFF signal, attenuated to an l8mv/octave level and applied to pin 15. The resonance is controlled by the voltage on pin 10, which is determined by three digital bits: RESA, RESB, and RESC. The diodes in the resonance control network assure that there will be a large jump between the maximum resonance control voltage (level 6) and the self-oscillation control voltage (level 7).
The filter output is on pin 17. It feeds back into the resonance circuit on pin 11 and forward into the output volume VCA on pin 12. The volume level is controlled by the level on pin 13 RX49 and CX29 slow changes in the volume down lust enough to prevent harsh clicks. The final output is a current that is steered by ZX08C into either MAIN OUT or ALT OUT.
ZX00 is the latch that holds the various digital control bits for the voice. It is written to by generating a WR SYN(N)/ strobe (from Z32). It is only written when one of the parameters contained in it is changed.
The Left Control Panel Board and Right Control Panel are best explained together, as the left one is really just an extension of the right one. The cable from the Main Board connects to the right board and that is where the address decoder for all control panel devices is located.
Z4 on the right board takes in three address bits, called A0, A1 and A2. These actually connect to address bus bits 1, 2 and 3 coming from the computer. This is because the computer has a 16-bit wide data bus, allowing it to read and write two consecutive memory or I/O locations at the same time; thus, bit 0 of the address bus selects which half of the data bus the data transfer takes place on. Since all I/O devices are on the low half of the data bus, all I/O addresses are even numbers, and address bit 0 is always a 0.
All data to and from the panel flows across an 8-bit bidirectional data bus, labelled B0 through B7. When the computer is outputting a byte or data to a device on the control panel these lines are driven by a buffer on the Main Board. When the computer is inputting a byte or data from a device on the control panel these lines are driven by that device. When the computer is neither outputting to or inputting from the control panel, all eight data lines, as well as the address lines, are tri-stated.
Z4 also accepts a strobe input called STB. This is a positive-going pulse that occurs whenever the computer reads from or writes to an I/O device on the panel. Whenever the computer performs a bus cycle that refers to a panel I/O device, the address lines (and data lines, if the operation is an output) are first driven with the correct information. Once this has stabilized the strobe pulse is generated. When the strobe pulse completes, the address and data lines are tri-stated again. The width of the strobe pulse is normally 250ns with an 8MHz clock (16MHz crystal) or 333ns with a 6MHz clock (12MHz crystal).
Z4 steers the strobe pulse to the appropriate device. Four outputs of this chip are used, numbered 0 through 3, corresponding to I/O addresses 0180, 0182, 0184 and 0186 (hex). No specific indication is given to the panel devices of whether an operation is input or an output. This, however, is not a problem, as each device has a separate I/O address and the computer never attempts to input from an output device or vice versa.
Reading the state of the membrane switches requires the use of two I/O devices. The switches themselves are organized into a matrix containing eight banks of eight switches each and five switch positions in the matrix are not used. The computer reads one bank of switches at a time by outputting a switch bank number (binary 00000000 to 00000111) to the I/O location 0184. The number 2 output of the strobe decoder (Z4-13) generates an active-low pulse which latches the bank number into Z2. The output of Z2 is connected to Z1 and causes one of its eight outputs to turn on. The outputs of this chip are open collectors to ground, so the selected output is connected to ground while the remaining outputs float.
Outputs 0, 1 and 2 of Z1 connect to the switches in banks 0, 1 and 2 on the left membrane switch, while outputs 3 through 7 connect to the switches in banks 3 through 7 on the right membrane switch. When a switch is closed, one of these outputs, designated SWSTBn/, will be electrically connected to one of the switch data lines, designated SWn/. Normally all eight of these lines are pulled high by R9 through R16, but a closed switch in the selected bank will pull one of these lines low.
The computer reads in the state of the switches in the selected bank by performing an input from I/O location 0186. This causes an active-low pulse to be generated by output 3 of the strobe decoder (Z4-12) and this turns on Z3, causing the eight data bits to appear on the data lines B0 through B7 where the computer can read them.
The software in the computer inputs all eight banks or switches in a short burst and this burst is repeated roughly every 12ms in an 8MHz system or 20ms in a 6MHz system. When the computer sees that a switch is closed that wasn't closed on the previous scan, it takes action based on that switch.
Each LED is driven directly by one of the outputs of one of the 74LS164 shift registers. These chips happen to have about the right output current for LED's and are very cost-effective. Each data line, B0 through B7, is connected to the data input on a shift register. Five of these are on the right board (Z7 through Z11) and the other three are on the left board (Z5 through Z7). All chips are clocked by the number 1 strobe from the I/O decoder.
When the computer outputs a byte to I/O location 0182, each bit in that byte appears on pin 3 of one of the shift registers and the bits in the shift registers move up one position. The data that were previously in the last bit positions, pins 13, are lost. The computer has a special instruction that allows repetitive outputs to an I/O location at full speed and this instruction is used to output eight bytes to location 0182. This causes all the data in the shift registers to be flushed and replaced with new data.
The strobe pulses that output to the LED shift registers occur every 1us in an 8MHz system or every 1.33us in a 6MHz system. Between the first and last outputs, the contents of the LEDS is incorrect, but this condition only lasts 7us in a 8MHz system, or 9.33us in a 6MHz system, and is therefore all but invisible to the human eye. The operation of outputting to all the LEDS takes place whenever any single LED or combination of LEDS needs to be turned on or off by the computer.
This section selects the voltage from one of the sliders or other analog inputs and connects it to the ADC line going back to the A/D converter on the Main Board. There are twenty-four analog inputs in the system and each one is selected by outputting a code to I/O location 0180. This causes output 0 of the strobe decoder (Z4-15) to generate an active-low pulse. The code is latched into Z6, which presents it to the mux (multiplexer) circuitry.
The mux consists of three 8-input mux chips; Z5 on the right board and Z3 and Z4 on the left board. The three lsbs of the code go to the A, B and C inputs on the mux chips, selecting one of the eight channels within each mux. The 3 msbs of the code each go to the enable input on one of the mux chips. One of the muxes is enabled by making one of these bits a 0 and the other two bits 1's.
Thus, exactly one of the analog switches in one of the mux chips will be turned on and the selected voltage will drive the ADC line. The sliders hang between the ADC GND and ADC REF lines, which are at 0V and +5V, as this is the range expected by the A/D converter.
Four analog inputs come from off the control panel. Buffers Z1A, Z1B, Z2A and Z2B are provided for these on the left panel. The LEVER 1 and LEVER 2 inputs are voltages that are derived from rotary pots in the lever assembly. Since only a small portion of the pot rotation is used, these pots are supplied with +12V, and the voltage they produce is roughly +1V to +4V, resting at around +2.5V. The PEDAL input expects to connect to a 100K pot to ground inside the optional foot pedal. This results in roughly a 0V to +4V range at the input to its buffer. The CMOS RAM battery is connected to the BATT line that comes from the main board through the right panel and is nominally around +3V.
Note that the buffer amps include transistors. Although the outputs come from the collectors, they are actually functioning in their inverted configuration as emitter followers. In this configuration, the emitters act as collectors and vice versa; the reason for this is historical and not very interesting. The circuits would work just as well with transistors connected normally. The main point of these transistors is that they allow the outputs to go exactly up to +5V, at which point they saturate; or down to 0V, at which point they cut off. Therefore, there is no danger of blowing out the mux inputs, even if the pedal is unplugged or a lever is mechanically misadjusted and producing more than +5V.
Note also that the buffers are FET input. This is particularly necessary in the case of the battery voltage buffer. Even when the power to these buffers is removed the input will not draw current even though it is sitting at around +3V.
The buffers have a zener diode in series with their minus supply to limit how far negative the output of the op-amp can go if the inputs should go negative. This is a precaution that is probably unnecessary.
Most power to the panel is carried by the DIG GND, +5V DIG, ANA GND, +12V ANA and -127 ANA. The LEDs are given their own power system, LED GND and LED +5V, so that their high current drain will not upset the ground reference used by the data, addresses and strobe. The sliders are also given a separate power system, ADC GND and ADC REF, so that varying current consumption in other parts of the system will not introduce jitter into the slider position measurements.
The AC power comes through a three-conductor grounded line cord. The chassis is connected to earth ground for the protection of the user and to minimize radio-frequency emissions. The receptacle on the rear panel includes an integral line filter connected to chassis ground. The power switch is a double pole switch that completely isolates the unit from the line when turned off, even if the grounding system has been defeated.
This small board to the left of the transformer includes a fuse, a voltage selection switch, and two MOV's (medal-oxide varistors) to clamp line transients. The switch connects the two transformer's primaries in parallel for 100V to 130V operation or in series for 200V to 260V operation. If you change the position of this switch, you must also change the fuse value. 3/4A or 800mA is the correct rating for the low-voltage setting and 3/8A or 400mA is correct for the high-voltage setting.
This board uses a SEMKO approved fuse and has jumpers installed in place of the voltage selection switch. The transformer primaries are permanently in series.
The power transformer has two identical primaries (as mentioned above) and two different secondaries, one for the digital supply and the other for the analog supply. It also has an electrostatic shield between the two that is connected to chassis ground for added protection and interference suppression. In the SEMKO version each secondary is fused on each side.
CR1 through CR4 rectify the voltage from one of the transformer secondaries and C1 and C2 filter it. C5 and C6 provide better high-frequency filtering, necessary for stable operation of the regulators. Four regulators are provided, all of them "three-terminal" types. The +12V, -12V and -5V supplies are fixed and the +5V supply is adjustable. Z3, a LM317, is a 1.2V regulator whose "ground" terminal (pin 1) draws very little current. By connecting pin 1 to a feedback network, the device can regulate to any voltage greater than +1.2V. The output voltage is made adjustable by making the feedback network adjustable.
C10, C12 and C15 provide additional filtering and stabilization; R26 provides a minimum load so that the negative regulators will operate correctly when the Main Board is disconnected.
CR5 and CR6 rectify the voltage from the other transformer secondary and C3 and C13 filter it. C15 filters the high harmonies of the diode switching to minimize interference generation. Z5 is an adjustable regulator that works on the same principle as Z3, except that has a much higher power rating. C14 provides output, stabilization. At the output of the supply, the digital ground is connected directly to the analog ground and through a 1M resistor to the chassis. This is the only place in the system the grounds are connected.
An additional rectifier, CR7 and CR8, is connected to the analog supply secondary and it is filtered by C4. This supply generates a positive voltage that is loaded to a negative voltage through R10. The time constant of C4 and R10 is such that when the power is shut off the voltage on C4 drops toward zero very quickly. The remaining resistors and transistors form a crude comparator circuit with hysteresis. When the AC input is turned on, the AC OK signal goes high pretty much with the +5 DIG supply that powers it. When the AC input is turned off, the AC OK signal goes low within a cycle or two of the AC input long before the +5 DIG supply goes out of regulation. This signal interrupts the computer on the Main Board allowing it to "put itself to sleep" in an orderly manner.
This circuit contains a precision 1.2V reference diode and a comparator circuit with an adjustable threshold and a small amount of hysteresis. Its purpose is to indicate whether or not the +5V DIG supply is within regulation. The comparator must be set so that it switches off when the supply falls to about +4.80V or 4.85V. When so set, the comparator will switch on when the supply rises to about +4.90V. The LED, CR10, allows the service technician to see the state of the output while adjusting the comparator.
The signal produced by this circuit, DC OK, connects to the RESET input on the computer, switches the CMOS RAM between battery and line supply, and gates the chip select lines to the CMOS RAM. When the Polaris is turned on the computer will not be allowed to function until the supply is within regulation and DC OK goes high. When the Polaris is shut off the AC OK signal will fall, as described above, and then the DC OK signal will fall, halting the computer.
When a channel is being tuned by the computer the output current produced by that channel alone is switched into the ALT OUT input to this board. Z1 converts this to a voltage whose amplitude is sufficient to drive the input to the timer circuit on the main board, but not so high that it will clip. The 100ohm resistors, R9 and R11, simply isolate the buffer input and output from the cable capacitance.
Normally, all channels' outputs connect to the MAIN OUT input to this board. In addition, the outputs of the click generators and cassette monitor circuits combine to drive the DATA AUD input. This DATA AUD signal from the main board has a +2.5V DC bias, which sets the bias for the input to Z2. Since the channel outputs are current outputs, they don't mind operating into this voltage level.
The sum of all the channel output currents pass through R5, which converts them into a small voltage, say 30mV or 40mV p-p. This voltage drives the input to Z2. Since the signal from the Main Board is a current, R4 has no effect on the voltage seen at the input to Z2, but it does help to reduce the noise pickup by increasing the impedance on the MAIN OUT line. R3 couples the DATA AUD signal in as well, C3 filters high-frequency trash that is everywhere in computer circuits, and C2 provides AC ground and DC blocking.
Z2 is an "operational transconductance amplifier" or OTA. It takes its input, which must be small, and multiplies it by the bias current fed into pin 5. The result appears as a signal current from pin 6. The bias current input looks like a diode to the minus rail of the chip. R14 and Q1 provide level shifting so that the computer can use a 0 to +5V signal to control the gain of this circuit. C4 and R6 provide filtering to the volume control signal, as any changes in it occur in discrete steps rather than smoothly. C5 provides additional filtering of any noise in the area, as pin 5 is fairly sensitive.
The output of Z2 is ideally a bipolar current signal with no DC component. However, due to offset error in its input, there is usually a slight DC component. R7 and C6 separate the DC and AC. Z2-6 should be between -2V and +2V; if it is outside that range, either there is DC at its input or it is a bad chip.
At any rate, the AC current passes through C6 into current-to-voltage converter Z3A. The fact that the signal passes as a current from the high-impedance output of Z2 to the low-impedance input of Z3A allows the final output to derive its ground reference from whatever external device it is connected to. The output jacks are floating with respect to the chassis and their sleeves are connected to the LINE RETURN, which is the ground reference to the output circuit. Thus, if there is a small amount of hum on the external device's ground, the hum will be duplicated at the LINE OUT, making it invisible to the external device.
The voltage at the output of Z3A is buffered by voltage followers Z3B, and Z3D. All four outputs are mixed through four 4.7 ohm resistors to provide the actual final output of the circuit. Offsets in the op-amps cause quiescent currents to flow through these, but these currents are generally less than a milliamp. C13 helps stabilize the circuit by allowing high frequencies to be fed back directly without having to go through the remaining op-amp sections.
The purpose of the extra buffering is so that the circuit can directly drive headphones. When driving the line output an additional 100ohm resistor is connected in series with the output to isolate the output from the potentially large capacitive load that a long audio cable would provide. R8 provides a ground reference for use when the external device provides none of its own, such as when headphones are used or when the output is transformer coupled at the other end.
Although this circuit can tolerate some common mode voltage at its output, too much would damage the op-amp Z3A. To guard against this, diodes CR1 and CR2 keep the LINE RETURN from getting more than a half volt or so from the chassis ground. C1 filters computer noise picked up in the output circuit.
Note that this output circuit is not designed to be used to drive a line output and headphones at the same time. If you try this you will find that the current drain of the headphones may cause clipping at volume levels that are too soft at the line output. In addition, any common mode voltage present at the device connected to the line output will be injected into the circuit and heard full-strength in the headphones.
This entire board is rather sensitive to noise pickup. C9, C10, C11, and C12 bypass the power supply and C2, C3, C5, and C7, along with the shielded input wires and careful layout, reduce the noise picked up from the air.