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Section 0

Service Manual: Circuit Descriptions

Main Sections

Computer Board

The Computer Board consists of the following sections, as outlined on the schematic:

  1. Clock generator
  2. CPU (central processing unit)
  3. Address decoder
  4. RAM
  6. EPROM
  7. CMOS RAM power switching

Each will be covered individually, in the following descriptions.

1. Clock Generator

The clock generator is a simple TTL crystal oscillator running at 16MHz. It feeds a divide-by-two flip-flop that produces a 2-phase 8MHz square wave, suitable for clocking both the 68B09 CPU on board and the 8039 keyboard scanning processor on the I/O board.

2. Central Processing Unit

The CPU circuit consists mainly of the 68B09 chip. Buffering is provided for the lower-order address lines, the control lines, and the data bus. The keyboard interrupt line (KINT) drives the fast interrupt request (FIRQ) line on the CPU. The external input and output interrupt lines (XIINT and XOINT) both drive the normal interrupt request (IRQ) pin on the CPU. The E and Q signals that emanate from the CPU consists of two 2MHz square waves in quadrature (90° out of phase), and these signals, "ORed" together by Z10A, provide a 75% duty cycle active-low enable signal that establishes the timing of each bus cycle. All on-board memories are connected to the CPU by the "direct bus" (D0 through D7). All off-board circuits are connected to the "buffered bus" (B0 through B7) which is isolated from the direct bus by a bus transceiver, Z2. This transceiver is enabled only when off-board devices are accessed. The circuit consisting of R44, R45, C31, Z8D and Z8F slightly delays the enable signal to the transceiver until the data output by the CPU chip is valid (during writes to off-board devices).

3. Address Decoder

The address decoder routes the 2MHz enable signal produced by Z10A to whatever device is being addressed during each bus cycle. The decoder is in two stages. The first stage consists of Z7, and routes the enable signal to one of its eight outputs depending upon the three most significant address bits. Addresses in the range 0000 (hex) to 1FFF cause an enable pulse to be generated at pin 15, addresses in the range 2000 to 3FFF pulse pin 14, etc. The second stage consists of Z5 and Z6. Z5 is activated by addresses in the range C000 to FFFF and routes the signal to one of the eight EPROMs on the board. (The R/W signal on pin 6 prevents any spurious write cycles from attempting to write into the EPROMs.) Z6 is activated by addresses in the range 0000 to 1FFF and routes the signal to one of the eight pairs of RAM sockets on the board. Pin 14 of Z7 is gated with both polarities of the R/W signal to produce IORD and IOWR. These signals activate the input/output devices on the I/O board. Note that all input/output is memory mapped in 68B09 systems.

4. RAM

The system uses 4K bytes of RAM for storage of data structures during operation. Eight 1K by 4 static RAM chips are used.


The system requires 3K bytes of non-volatile storage for the synthesizer "programs." This is provided by six 1K by 4 static RAM chips. These chips have their own VDD line which remains powered when all else is shut off. Each transistor circuit functions as an isolator for the chip selects. When RESET is low (which it naturally is when the power is shut off) the transistors allow the chip select (CS) inputs to the CMOS RAMs to rest high (inactive) even though the enable signals from the address decoder are all low.


The firmware that controls the operation of the 68B09 processor amounts to almost 16K bytes. This is contained in eight 2K by 8 EPROMs. Their only peculiarity is that they are read-only devices. Hence the W/R line is used to disable them during write cycles.

7. CMOS RAM Power Switching

This circuit contains two AA cells, which provides power to the CMOS RAMs when the instrument is turned off, and two transistors to select between the battery and the main power supply. When the instrument is off, the battery is supplying a few volts. This is applied through the germanium diode CR1 to the CMOS RAMs. Since the rest of the circuit has no power, everything else is at 0 volts, meaning that Q1 and CR2 are reversed biased. As soon as the main power starts to rise above the battery voltage, CR2 becomes forward biased and CR1 becomes reversed biased. Now the CMOS RAMs are being powered from the main supply. However, the drop across CR2 can be nearly a volt under load. When the system RESET signal disappears (goes high), Q2 and Q1 turn on, shorting out CR2 and applying the full 5 volts to the CMOS RAMs. Capacitor C3 slows down this final transition to 5 volts. When the power shuts down, the process is reversed, and the first thing that happens is the arrival of the system RESET signal. CR2 is a power diode because the CMOS RAMs consume significant current during operation. CR1 is a germanium diode for its lower voltage drop. (Also, it leaks about 10uA when the main power is on, trickle charging the batteries.)

I/O Board

The I/O Board consists of the following sections, as outlined on the schematic:

  1. I/O Strobe Decoder
  2. Keyboard Scanning Computer
  3. Computer Interface
  4. Timer
  5. A/D Converter
  6. D/A Converter
  7. Switch/Display Matrix
  8. Cassette I/O
  9. Cassette Motor Sense/Control
  10. LED Drivers
  11. Tapper Driver
  12. Miscellaneous I/O

Each will be covered individually in the following descriptions, with particular attention paid to the keyboard scanning computer and the timer.

1. I/O Strobe Decoder (sheet 1)

The main computer selects each device it wants to communicate with by using the I/O strobe decoder and the data bus. Whenever the computer wants to read a byte (8 bits) of information from any device not located on the computer board, it activates the IORD line by bringing it low for 375ns (nanoseconds). During this time, the address bits A0, A1, A2 and A3 will contain a number that identifies the device that the computer wants to read data from. The decoder (Z39 for reads) generates a pulse on one of its eight outputs that looks just like the IORD pulse: active-low TTL level, 375ns wide. In other words, the decoder steers the master IORD pulse from the computer to one of eight devices. Each individual RD pulse causes the appropriate device connected to the data bus to turn on its output drivers. At the instant the IORD pulse is over, the computer samples the data on the bus.

The computer writes data to devices in a similar manner, although of course, the direction of the data flow is the opposite. The computer will activate the IOWR line for 375ns, and during this time the four address bits will contain a number identifying the device that the data is to go to. The decoder chips (Z40 and Z41 for writes) steer this pulse to one of 16 places. Meanwhile, the computer also drives the data bus with data. Each WR strobe line causes the appropriate device to sample the data bus and pick up the data.

All communication between the computer and the "outside world" is performed by time-sharing or multiplexing data over eight bus lines, and each byte of data takes 375ns to transfer. (There is an additional 125ns idle time between bus cycles, which means that the bus can transfer data at up to 2 million bytes per second.) In order to "see" what's going on in a computer system, it is necessary to examine the data bus during a specific time slot, not just all the time. If you look at a data bus line with an oscilloscope (without triggering off anything in particular) you will not see anything meaningful. Debugging such circuits require as an absolute minimum a dual trace oscilloscope with enough bandwidth to trigger off and see submicrosecond events. The technique is to use one trace to trigger off and view one of the RD or WR strobes, and then use the other trace to examine each data bit in turn to see whether it is at a logic 0 or 1 at the trailing edge of the strobe.

The three decoder chips thus provide eight read strobe lines and sixteen write strobe lines. After the first small production run, it was decided that one more bit of input to the computer was required. Z55, a triple three-input open-collector NAND gate was added to sense the EOC (end-of-conversion) output from the A/D converter. Whenever the computer performs a read from location 2008 hex, address bit A3 will be high during the IORD pulse, This will cause data bus B7 to be pulled low if the conversion is not complete.

2. Keyboard Scanning Computer (sheet 1)

The keyboard scanning in the Chroma is performed by a separate processor, an Intel 8039. This processor has its own local data bus (DB lines, pins 12 through 19) which connects the 8039 to its program memory (EPROM Z33) and to the keyswitch boards. The operation of this data bus is similar to the operation of the main data bus, except that there is no separate address bus. Instead, there are four control signals associated with the bus that control the timing of all data transfers in and out of the 8039. All bus cycles begin with the 8039 asserting ALE (Address Latch Enable, an active high pulse). During the pulse period, the bus will contain an address. (Certain bits in port 2 are also used, but the keyboard scanning firmware only requires 8 address bits.) The address latch (Z32) is responsible for holding the address during the data transfer portion of the cycle. Shortly after ALE goes low, the data transfer commences, under control of one of three active-low strobe lines, PSEN (program store enable), RD and WR.

This particular circuit uses PSEN to enable the EPROM containing the keyboard scanning firmware. It also uses the RD strobe to fetch data from the keyswitch boards, but it uses this strobe in an unconventional manner. The keyswitch boards accept a 4bit code that selects one of 16 banks of keyswitches, and returns eight lines corresponding to the switches within the selected bank. The amount of time it takes to return this data is too long for the entire communication to take place within one bus cycle so it is done in two. The firmware actually reads two banks of switches in a row, an A bank and a B bank for a particular group of eight keys. A total of three cycles are used. In the first cycle, the computer supplies the number of a bank on the address lines, strobes RD, and ignores the data that it receives. This effectively writes the data to latch Z35 which drives the keyswitch boards. On the second cycle, it supplies the number of the second bank on the address lines, strobes RD, and reads in the data from the previous bank. The number of the second bank is latched by Z35. On the third cycle it reads the data that returns from the second bank.

The keyboard scanning computer scans the keys about 1000 times per second. It measures, for each key, the time between the opening of one switch contact and the closing of the opposite contact in millisecond increments. Whenever a contact closes, the key number and the time measurement is sent to the main computer. The port pins (P1 and P2) on the 8039 are used for this purpose. Whenever information is to be transmitted to the main computer, the 8039 supplies the time measurement on port 2 bits 6-0 (pins 21-24, 35-37). Bit 7 (pin 38) will be high for a release and low for an attack. It then puts the key number (from 0 to 63) on port 1 (pins 27-34) and then sets pin 34 high. Thus pin 34 produces a short negative-going pulse whenever new information is present. The two NAND gates (Z49) form a set/reset flip-flop that performs interrupt handshaking between the two computers. Whenever information is sent by the 8039, the pulse from pin 34 sets the flip-flop to one state, bringing KINT low and interrupting the main computer. The main computer temporarily suspends what it is doing and reads first the key number, and then the time measurement by activating the RD NOTE and RD VEL strobes. The RD VEL strobe sets the flip-flop to the opposite state, clearing the interrupt.

Note that the interrupt line KINT also connects to the interrupt pin (INT, pin 6) on the 8039. This does not interrupt the 8039. Instead, this pin is used by the keyboard scanning firmware to check to see if the previous data transfer is complete. The K MASK line serves a simple purpose during auto-tune and cassette operations. When low, it holds the flip-flop on its reset state (Z49-8 high). This causes any keys played on the keyboard to be ignored by fooling the 8039 into thinking that its interrupts are being immediately handled. Thus, any notes accidentally struck while the Chroma is in auto-tune, for instance, will not "pile up" and suddenly be heard when the auto-tune is complete.

The only other details of the keyboard scanning circuit are the clock lines. The 8039 gets it clock in two-phase form at 8MHz from the main computer, so both computers are actually synchronized. This synchrony isn't important to the operation, but does save the cost of another crystal oscillator. The port 2 lines emanating from the 8039 are not static lines, and as such, have to be latched (whereas the port 1 lines are perfectly static). The port 2 data is always valid during the rise of ALE, and so the ALE signal is used to clock the data onto latch Z36. The ALE signal, which run at about 500KHz, is also used as a clock signal for the A/D converter, as it is a convenient frequency.

3. Computer Interface (sheet 1)

The computer interface consists of an 8-bit input port with handshaking and an 8-bit output port with handshaking. If you are wondering what the port might connect to, imagine it connected to an exact duplicate of itself; that is, imagine each input port line (mnemonics starting with XI) connecting to the corresponding output port line (mnemonics starting with XO) at the other end of the interface. The interface only consists of the output latch (Z26), the input tri-state driver (Z27) and the five NAND gates (Z48, 49). The rest of the circuit is just for noise rejection and isolation when the power is shut off. When the Chroma wants to transmit a bye of data, it checks the XO FULL line to see if the last byte it send has been received yet. When it has, it writes the byte into the latch with the WR EXTO strobe. This causes the flip-flop consisting of gates Z48-A and Z48-B to be set, and pulls the XO FULL line low. This tells the computer that the output port is full (and not to send any more data yet) and tells the other end of the interface that there is fresh data to be had. When the other end reads the data, it will pulse the acknowledge line XO ACK, which resets the flip-flop and resets XO FULL high (inactive) again. This tells the computer that it can send another byte of data. The input interface performs the other side of the same task. When data arrives from the other end via the XI lines, the XI FULL line will go low, telling the computer the fresh data has arrived. When it reads it, using the RD EXTI strobe, the acknowledge XI ACK will be pulsed, causing the flip-flop at the other end to be cleared, and causing XI FULL to go high (inactive) again.

The remaining gates are used to generate interrupts. Normally, the Chroma is ready to accept data from the interface, and the XI MASK line is high (inactive). This means that an incoming byte, which is accompanied by XI FULL going low, will cause XI INT to go low, interrupting the main computer. The only time the computer activates XI MASK to prevent input interrupts is during auto-tune and cassette operations, or if the device at the other end of the interface is sending data faster than the Chroma can process it. Normally, the Chroma has no data to transmit, and if it does, the interface is usually ready for it, as signified by a high (inactive) XO FULL. If, however, the Chroma has data to send and the output port is still full from the previous data transfer, the Chroma will only wait a short amount of time before it decides it has better things to do than wait around. When this happens, the Chroma will stash the byte of data in a FIFO (first in first out) queue in its memory and set XO MASK high (inactive), thus unmasking output port interrupts. The output port interrupt (XO INT) occurs whenever the device at the other end of the interface gets around to reading the data off the interface and sending back an XO ACK pulse. Then the Chroma will take time out from whatever it is doing to pull a byte from the end of the FIFO queue and output it. Only when the queue is empty does the main computer mask output interrupts again by setting XO MASK low (active).

4. Timer (sheet 1)

The Chroma uses a timer implemented with TTL MSI (medium-scale integration) parts, as there are no LSI (large-scale integration) timer chips available that perform the specific functions needed. The timer consists mainly of a 16 bit resettable counter running at 2MHz (Z44 and Z45), a 16 bit latch (Z46 and Z47) and a status flip-flop (Z50C and Z51B). The rest of the circuit simply connects these basic elements to various signals. The timer has five operational modes that the Chroma uses under different circumstances. The timer mode is set, and the timer's operation is started, by writing the appropriate number to the timer mode latch (Z42). The modes, as reflected in a binary number that appears on pins 7, 14 and 2 of Z42, are as follows:

0. 1024us mode -- used to regulate the speed of the main software loop during normal operation.

1. Tape mode -- used to measure the period of the signal received from the cassette during LOAD ONE and LOAD ALL operations.

2. Synth mode -- used to measure the period of the synthesizer signal during auto-tune.

3. Synth/64 mode -- used to measure the accumulated period of 64 cycles of a high frequency during auto-tune.

4. 416us mode -- used to regulate the frequency of the cassette signals generated during SAVE ONE and SAVE ALL operations.

Each mode shares the same timing resources: a re-settable counter, a latch, and a status flip-flop. What differs is how they are connected together.

0: 1024us Mode

This mode is used to regulate the speed that the Chroma repeats its calculations for each synthesizer channel. If the currently selected program contains little modulation, the amount of time the computer will take to compute each sample of the control signals may only be a few hundred microseconds. In a very complex program, the computing time is much longer, although it doesn't often get any longer than a millisecond. When the computer begins the calculations, it sets the timer mode to zero. The write pulse, WR TMOD, also resets the counter to zero through Z50A and sets the flip-flop not ready (TRDY high). The timer is designed so that the current count will be latched and the counter reset whenever a negative pulse comes out of either data selector (Z43A or Z43B). In mode 0, this occurs when the counter reaches a count of 2048 and Z45-5 goes low. The falling edge of this signal is differentiated by R58, R65 and C18 into a very narrow pulse 9about 50ns) which is routed through data selector Z43B. When the computer has finished its calculations for a particular synthesizer channel, it polls TRDY until it goes active (low), signifying that the 1024us time has expired.

1: Tape Mode

This mode is used during cassette load operations to measure the signal received from the cassette. The cassette uses a simple FM (frequency modulation) scheme operating at 1200 baud (bits per second). A 1 bit is represented by a full cycle of 1200 HZ and a 0 bit is represented by a half cycle of 600 HZ. Thus, a 1 bit is received as two 416us periods between zero-crossing and a 0 bit is received as a single 833us period between zero-crossings. The tape signal is presented to the timer as two signals, one being the inversion of the other. Each signal is connected to a differentiating network to generate a tiny negative-going pulse on the fall of the signal. Since the two signals are out of phase, a pulse is generated on one edge by one RC network and on the other edge by the other RC network. The data selectors route these pulses into the timer where they cause the current count to be latched and the counter to be reset. When the computer senses that the time is thus ready (TRDY low), it reads the two-byte time value (RD TIME and RD TIME+1). The RD TIME strobe automatically sets the timer not ready again (via Z50 pin 10) even while the next time period is being measured.

The leftmost bit of the counter (Z45 pin 9) is fed through its own differentiating network back to the status flip-flop. This is in case the cassette (or auto-tune) isn't generating any signal. When the timer overflows its maximum count of 32767 (about 16ms), this line causes the status flip-flop to be set ready and 0 to be latched as the time value.

2: Synth Mode

This mode functions similarly to the tape mode, except that the entire period of the incoming signal (in this case, from a synthesizer oscillator or filter) is measured, instead of the time between successive zero-crossings. In other words, the timer need only be latched and reset on falling edges of the incoming signal. Therefore, only one phase of the signal is used. Data selector Z43A selects the differentiated falling edge of the signal. The auto-tune routine first selects this mode (which always sets the timer not ready) and waits for it to become ready. Meanwhile, it refreshes all the sample-and-holds on the synthesizer channels. When the timer becomes ready, it reads in the two-byte value. If the value is 0, it assumes that the channel isn't functioning properly and that the timer overflowed. If the value is non-zero, the channel is probably making sounds but the reading still isn't valid, as it isn't referenced to anything. However, reading the time value sets the timer not ready again, so, without resetting the timer mode, the auto-tune waits a second time for the timer to become ready. When it's ready this time, the reading will accurately reflect the amount of elapsed time since the previous reading.

3: Synth/64 Mode

This mode is exactly like the previous mode, except that the signal whose period is being measured comes from a six stage binary counter (Z11). This counter functions as a prescaler for measuring high frequencies produced by the synthesizer channels during auto-tune.

4: 416us Mode

This mode functions exactly like the 1024us mode with one difference. Since the mode number is 100 in binary (as compared to 000 for the 1024us mode), the line from Z42 pin 7 to Z51 pin 13 is high in this mode. The four-input NAND gate (Z51A), when thus enabled, produces a negative-going signal when the count reaches a count of 832. This is routed through data selector Z43A to set the timer ready. During cassette saves, the computer waits for the timer to be ready, performs the necessary serial output, and then reads the timer (to set it not ready without resetting the counter). Thus, the serial output occurs at a 2400Hz rate. To output a 1 bit, the computer outputs 2 consecutive transitions. To output a 0 bit, the computer leaves out the first transition, generating a half cycle at half the frequency.

5. A/D Converter (sheet 2)

The analog to digital converter is responsible for measuring the physical position of the two levers, two variable positions, and the TUNE and PARAMETER CONTROL sliders on the panel. It is also wired up to measure the voltage from the pressure sensor assembly or from the CMOS RAM battery. The circuit consists mainly of an ADC 0809 converter chip, which is a CMOS device that operates on a single 5V supply. It includes an on-board 8-input multiplexer for selecting one of eight analog voltages, an 8-bit D/A converter and successive approximation register. The computer selects a voltage to be measured by writing a number to the A/D converter (WR ADCO is on the strobe). This activates the ALE input on the chip which causes the channel select number to be latched. The same strobe also activates the start conversion (SC) input to the chip. In order to allow the analog signal time to settle internally, the computer repeats the strobe 2.5us later, just to make sure. Then the computer goes off and performs other functions while the converter converts the voltage (which must be between 0 and 5 volts) to a number between 0 and 255. This takes about 150us. The computer eventually comes back to it and reads the converted value using the RD ADCI strobe.

The inputs to the A/D converter are all buffered by op-amps. The levers produce a voltage swing that's only about 0 to 2 volts, so the lever inputs are amplified. The pedal inputs require a pullup resistor, as the pedals contain nothing more that a potentiometer to ground, but these levels need no amplification. However, all these signals need to be clamped so that they don't exceed 5V. The transistors on the op-amp outputs provide this function, as they are powered from 5 volts while the op-amps are powered from 12V. This scheme is used because the voltage would otherwise definitely exceed 5V. The TUNE and PARAMETER CONTROL slider inputs come from sliders that are "hung" between 0 and 5 volts, because they don't require accurate clamping. There are, however, diodes on the slider buffer op-amp outputs to protect the A/D against catastrophic op-amp failure. The pressure input is buffered off-board. The remaining input, which comes from the battery, is buffered with a FET-input op-amp for two reasons. First, the op-amp input must not drain the battery. Second, when the power is shut off, the input must not pull the battery voltage down. The P-channel JFETs used in the op-amp allow the input to exceed the positive rail of the device without conducting current.

Z55A inverts the EOC (end of conversion) signal generated by the A/D converter chip and delivers it to the other two sections of Z55, shown on sheet 1 immediately above the I/O Strobe Decoder. This IC was added following the initial pilot production run to provide a means for the computer to sense if an analog to digital conversion is successful. A particular quirk of the 0809 converter chip is that it occasionally doesn't work! Since this is pretty much a random occurrence, rarely happening for two conversion in a row, the computer handles it by simply ignoring the bad conversion. Since each analog input is measured fifty times a second, occasionally doing on forty-nine conversions doesn't cause any problems.

6. D/A Converter (sheet 2)

The digital to analog converter generates all the voltages that are needed to control the analog circuits on the synthesizer channel boards. The main DAC (Z24) is a 12-bit DAC that uses a FET-input op-amp for an output buffer. Since one lsb (least significant bit) change corresponds to about 1.25mV, it is necessary that the op-amp offset voltage be well below this level. A null trimmer is provided, and can be adjusted by putting a DVM (with 100uV resolution) between the two test points and adjusting for zero.

With a -5 volt reference on pin 17, the range of the DAC would be 0 to +5 volts (it inverts). The reference voltage can, however, be "trimmed" under computer control by the use of the other DAC, Z20. This 8-bit DAC has a reference of +5 volts and hence produces an output of 0V to -5V. Op-amp Z21B and associated resistors reduce this range to approximately -4.4V to -5V. If the 8-bit DAC is centered, the reference to the 12-bit DAC will be about 4.7V. The oscillators and filters are scaled such that each step of the 12-bit DAC value corresponds to a 32nd of a semitone in pitch, which is a nice easy number for a computer to deal with. (Perfect semitone scales can be generated by counting with the five least significant bits set to zero.) However, no analog circuit is perfectly accurate. In conventional analog synthesizers, trimmer potentiometers are provided to adjust the scale factor of the pitch (so that an octave is really an octave). In the Chroma, this trimming is done by the computer by outputting the appropriate number to the 8-bit DAC. Of course, tuning offset can be corrected for by adding or subtracting a constant from the number sent to the 12-bit DAC.

There is nothing fancy about the DAC circuit. The 8-bit DAC uses two CMOS 4-bit latches for its data, which are written into by the computer with the WR RDAC strobe. CMOS latches are used because the 7523 DAC requires higher than TTL voltage levels. The 12-bit DAC occupies two bytes in the computer's address space. the four most significant bits are written into with the WR MDAC strobe. The remaining bits are written into with the WR MDAC+1 strobe. TTL latches suffice with 7541 type DACs.

7. Switch/Display Matrix (sheet 2)

The 71 switches and 80 display segments on the Chroma panel are arranged in matrices. The 10 "columns" of the matrix are driven by the outputs of Z13, a BCD-to-decimal decoder with high-current open-collector outputs. The computer can select a bank of switches and a display digit by writing a number into latch Z17 (using the WR SDS strobe). The computer can then turn on any segments in the selected digit by writing a pattern of bits to latch Z15 (using the WR SEGS strobe). The two large digits (I1) require the full drive capability of the decoder and latch, but the small digits (I2) require less current. (Note that the latch is S-series Shottky, not LS.) This is the purpose of the resistor network Z14. The computer multiplexes the display every 20ms in 16 time slots (each slot being 1.25ms). The small digits are lit in time slots 0 through 7, and the large digits alternate back and forth during time slots 8 through 15.

The computer can read the selected switch bank by reading from tri-state driver Z16 (using the RD SWB strobe). To guarantee that the switches can be read correctly, the computer only reads the switches in the brief intervals between the illumination of each display digit. The sequence, which only takes a few micro-seconds, consists of turning off the display (writing 0 to Z15), selecting the next digit and switch bank (writing to Z17), inputting the switch bank data (reading from Z16), and turning on the next digit (writing to Z15). The firmware compares each switch bank reading with a memory image of what the bank looked like last time it was read. This allows the computer to detect the initial depression of a switch independent of how long it is held.

8. Cassette I/O (sheet 2)

The square waves generated by the computer (TAPE OUT) are attenuated by R21 and R20 to a level suitable for feeding into a microphone jack on a cheap cassette recorder. The signal that comes back from the earphone output of the recorder during playback is much stronger, but only vaguely resembles the original signal and must be squared up again. Comparator Z8 performs this. Note the large amount of positive feedback necessary to clean up the signal. The D-flip-flop (Z10A) synchronizes the signal to the 2MHz clock (so that it will work correctly with the timer) and provides the necessary complementary versions of the signal for detecting positive and negative edges.

9. Cassette Motor Sense/Control (sheet 2)

This circuit uses a dual opto-isolator to isolate the Chroma circuitry from the voltages used to drive the cassette motor. When the MOT OUT signal is driven high, opto Z9A turns on, which, if there is any voltage in the motor circuit, turns Q2 on, allowing the motor to run. There will be a significant drop between MOTOR+ and MOTOR-, due to the Vbe drop of Q2, the diode drop of CR30, and the saturation drop of the transistor in Z9A. But this voltage is what allows the other half of the circuit to sense the state of the cassette recorder controls. If the cassette is set to STOP (or there is no cassette connected), obviously there will be no voltage on the MOTOR lines. Thus, opto Z9B will be off, and Q3 will be off, and MOT IN will be high. If the cassette recorder is turned on, but the Chroma's control of the cassette (Q2) is off, the full motor voltage (usually 6 volts or so) will appear across opto Z9B and FET Q10. The FET functions as a resistor, allowing enough current to flow to turn on the opto and Q3 and pull down MOT IN, but not enough for the motor to turn. If the Chroma computer decides to let the cassette run, it turns on Q2, but there is still enough of a voltage drop across the circuit to turn on opto Z9B and hold MOT IN down. This is because the FET acts as a nonlinear resistor, with a lower resistance at lower voltages (nearly a constant current sink). This arrangement allows the computer to sense whether the cassette controls are on or off, independent of whether the Chroma is allowing the cassette to actually run.

Diode CR31 is there to protect against inductive kick-back when the motor is turned off. Capacitor C6 is there to slow the rise of MOT IN way down. This is necessary because a cassette recorder operated from AC with no batteries installed usually runs its motor off unfiltered rectified AC. Were it not for C6, the MOT IN line would toggle 120 times a second.

10. LED Drivers (sheet 2)

The sixteen LEDs on the panel are driven from two latches (Z5 and Z6) that can be written into using the WR LEDS and WR LEDS+1 strobes. Using LS latches as current sources directly driving the LEDs (with only the internal latch resistance to limit the current) yielded a reasonable brightness, without wasting board space for 16 resistors. All blinking of the LEDs is performed by the computer. Z5 is only strobed when a panel switch is pressed. Z6 is strobed several times a second, as it drives the LEDs that must flash.

11. Tapper Driver (sheet 1)

Since membrane switches provide no tactile feedback, a solenoid tapper is provided in the Chroma. Whenever the WR TAP strobe is activated, flip-flop Z38A is set. This turns on Q1 and applies a hefty current from the unregulated power supply to the solenoid. Rather than have the computer turn the transistor off 20ms later (that's about 3 months in computer time), a feedback network is provided that makes the flip-flop function as a crude one-shot. R52 provides the negative feedback that ultimately resets the flip-flop. Capacitor C20 provides the time constant. And connecting the other side of C20 to the opposite output of the flip-flop (rather than to ground) provides some positive feedback to make sure that the switching is clean. Diode CR23 protects against inductive kickback when the solenoid shuts off.

Obviously, there is no direct connection between the panel switches and the tapper circuit. Instead, pressing a switch causes the computer to execute a certain part of its program that handles the appropriate switch function. One of the instructions in each switch handler is an instruction that writes to the memory location that corresponds to the tapper, activating the WR TAP strobe. The tapper can be disabled from the panel, but this is not done electrically. Rather, the location that the computer writes to is changed so that the tapper won't be triggered.

12. Miscellaneous I/O (sheet 1)

There is a 6-bit output port (Z30) that is strobed by WR PRSS. This latch is used to select one of the 64 keys on the keyboard and deliver the voltage from its pressure sensor to the PRESS input on the A/D converter. There is also an output port strobed by WR MSCO that contains miscellaneous output bits. Latch Z29 is activated by this strobe, and drives the three interrupt masks, the cassette data output and the cassette motor control. The same strobe also goes to the Channel Mother Board, where two more bits are latched from the B0 and B1 data bus bits. When the computer strobes RD MSCI, it reads in eight miscellaneous input bits, including the state of the external computer interface ports, the timer, the cassette motor sense, the LOCK switch on the rear panel, and the three footswitches. There are also three other strobes that go to the Channel Mother Board via Z41. The WR SHA strobe is used to write a sample-and-hold address into a latch. The WR SYND strobe is used to write 6 bits of data destined for one of the synthesizer channels into a buffer latch. The WR SYNA strobe is used to transfer the contents of the buffer latch into any of the 24 latches on the individual channel boards.

Dual Channel Board Circuit Descriptions

Each Dual Channel Board in the Chroma consists of the following sections, as outlined in the schematic:

  1. Sample and hold bank
  2. Data latches
  3. Oscillators (A and B)
  4. Filters (A and B)
  5. Amplifiers (A and B)

Each section will be covered individually in the following descriptions, except that the B channel circuits will only be described as they differ from the A channel.

1. Sample and Hold Bank (sheet 2)

This circuit consists of eight sample and holds and their associated switching logic. These sample and holds each employ two holding capacitors separated by a resistor, allowing the output voltage produced to be filtered, avoiding sudden step changes. A particular output is set to a voltage by applying the desired voltage to the DAC input, putting the appropriate sample and hold address code on the three SHA lines, and bringing SHEN low to enable the selected sample and hold. This causes one of the channels in Z19, a 4051 CMOS switch, to turn on, connecting the DAC voltage to one of the 0.033uF capacitors. This voltage doesn't immediately appear at the corresponding op-amp output, as it must first go through a low-pass network consisting of a 1M resistor and 0.0068uF capacitor. This slows down the sudden transition that could be caused if the current sample is different from the previous sample applied to this channel. The Chroma computer enables each sample and hold about 50 times a second. The filtration due to the resistor and second capacitor in each channel allows the Chroma to generate rapid portamentos and envelopes without the listener being able to hear that they are comprised only of a few discrete steps.

It is often necessary for the computer to change a particular voltage instantly. This is used for pitch changes without portamento, envelopes with sharp attacks, and trills. The computer can cause any individual sample and hold to produce a sudden, unfiltered, change in outputs voltage by merely bringing the FAST line low during the sample period. Z25B functions, in this circuit, like an OR gate: if FAST is low and SHEN is low, Z20's enable line will also be low. Thus, there will be a switch turned on in both Z19 and in Z20, connecting the DAC voltage to both capacitors in the selected sample and hold. Since both capacitors are thus charged to the desired voltage, there will be no filtering effect on the control signal.

The computer leaves each sample and hold selected while it calculates the voltage level to be sent to the next sample and hold. This allows somewhere between 150us and 500us for each sample and hold to acquire the DAC voltage. There are 64 sample and holds in the Chroma, and they are sampled in order of board number, board 0 first, and, on each board, in the order that they appear in the schematic, producing the PITCH A signal first and the VOLUME B signal last.

2. Data Latches

There is a 6-bit data "bus" that connects to all the Dual Channel Boards. This bus is not the same as the main system data bus, as the bus is too noisy to bring up onto the channel boards. This 6-bit bus is loaded with data by the computer whenever it wants to set any of the data latches on any channel board. Once the data is set up, either the STB0, STB1 or STB2 line will be given a pulse, writing into the appropriate latch. Most of the latch bits connect directly to various places within the channel circuits. The two leftmost bits are decoded to produce an active-low level on one (or none) of three lines, SYNC, RING MOD or FILT FM.

The SYNC, RING MOD, FILT FM and PATCH bits are updated whenever the Patch parameter is changed. The OUT bits are updated whenever the Output Select parameter is changed. The WAVE, MODE and RES bits similarly correspond to the Wave Shape, Filter LP/HP and Resonance parameters. If the Patch parameter is 0 in the program that is controlling a particular board, the 0 and 1 latches (Z28 and Z27) will both be controlled by the same "A" parameters. If the Patch parameter is non-zero, the A and B channels are controlled independently.

3. Oscillators (sheet 1)

EXPO CONVERTER. Z1 and Z4, and associated Rs and Cs form two identical garden-variety expo converters. They accept linear control voltages (from the PITCH A and B sample and holds) in the range of 0 to 5 volts and produce an exponentially controlled current ranging from 120uA down to about 100nA. These circuits have negative control, meaning that the highest oscillator pitch is attained at the lowest control voltage. The scaling is such that the output current (Z1-1 or Z1-11) changes by a factor of 2 (and the pitch changes by an octave) as the control voltage changes by slightly less than 0.5 volts. Thus, the oscillator has a typical range of somewhat more than ten octaves.

CHARGE PUMP OSCILLATOR. The design of the oscillators themselves is unconventional in the domain of electronic music, but have been around in the field of data acquisition for years. They are called "charge pump voltage-to-frequency" converters. The basic oscillating element is a 4151. It consists of a comparator, a one-shot, and a switched precision current source. Basically, the current from the expo converter is integrated by op-amp Z5 and capacitor C3 (or C4), causing the op-amp output voltage to ramp upwards at a rate proportional to the control current. Pins 6 and 7 on the 4151 are the comparator inputs. When the op-amp output, which drives pin 7, reaches 5 volts, the voltage on pin 6, the one-shot inside the 4151 is triggered. So far this is just like any other synthesizer oscillator; but most synthesizer oscillators use the one-shot output to essentially short circuit the integrating capacitor, forcing the output back to zero. Ideally, this discharge, or retrace, should happen instantly, as it is not "taken into account" by the circuit in determining the rate of oscillation. Unfortunately, it is never instantaneous, and at high frequencies this retrace time can appreciably lengthen each cycle, causing the characteristic "high-end drop" that most synthesizer oscillators have compensating adjustments for.

A charge pump oscillator does not use the one-shot to force the integrating capacitor back to zero volts, but rather uses the one-shot to pump a fixed quantum of charge into the capacitor in the opposite direction than the steady current from the expo converter. This fixed charge is created by turning on a constant current source for a fixed amount of time. In this circuit, the one-shot time is quite long compared to other synthesizer oscillator retrace circuits, about 20us. This is acceptable because the retrace time is inherently perfectly compensated for. At low frequencies, the charge pump (which, by the way, comes out pin 1 of the 4151) is adjusted by means of a trim to kick the integrating capacitor voltage back to exactly zero volts. At high frequencies, this charge is "working against" higher currents from the expo converter, and so the retrace, which is allowed the same amount of time, doesn't kick the capacitor voltage all the way back to ground. This compensates for the extra time spent retracing.

The linearity of this circuit can be easily proven by reasoning that the total current from the expo converter during each cycle must exactly counter-balance the total current from the charge pump during each cycle. If it didn't, the integration in each cycle would not wind up at the same 5 volt level. Thus, the following identity holds:

Since the frequency is the reciprocal of time:

In other words, f is proportional to lexpo. Look at it on an oscilloscope if you can't visualize it.

The output of the oscillator on Z5 pin 1 (or pin 7) is a sawtooth whose retrace is rather slow compared to most synthesizer oscillators. Pin 3 on the 4151 is an open collector that turns on during this retrace period. Thus the voltage on the right side of R17 (or R18) is a sawtooth with a very fast retrace.

SYNC CIRCUIT. The B oscillator differs from the A in that it is provided with a method for hard synchronization. The three discrete transistors, Q1, 2 and 3 provide this function. Whenever the A oscillator's cycle completes, its sawtooth output snaps from 5 volts back to ground. This sudden transition is differentiated by C19 and R79 and fed as a very narrow pulse through Q1 to the base of Q3. When this occurs, Q3 shorts out integrating capacitor C4, resetting oscillator B to the start of its cycle. If, however, the SYNC control line from the data latch is high, Q2 will be saturated on, its collector will be at about 0.7 volts, and the tiny pulse will be absorbed without passing through Q1. Resistor R81 keeps Q3 solidly off except during synchronizing pulses.

PULSE COMPARATOR. Resistors R19 (or R20) and R21 (or R22) mix the sawtooth produced by the oscillator with the pulse width control voltage from WIDTH A (or B) sample and hold. This signal is compared to a fixed 2.5V reference by comparator Z6. (The feedback components are simply to prevent oscillations at the transition point.) Since the sawtooth and the pulse width control voltage are both 0 to 5 volt signals, the input to the comparator on pin 2 (or 6) will be a 2.5Vp-p sawtooth whose average level can be adjusted from 1.25V to 3.75V. Thus, the comparator output will be a pulse whose duty cycle is variable across the entire range from 0 to 100%.

WAVE SHAPE SELECTOR. CMOS switch Z8 (or Z9) selects one of four wave shapes. The upper two are, obviously, the pink and white noise signals that are produced on the Channel Mother Board. The lower two inputs select oscillator signals. Pin 5 is provided with a combination of the pulse signal, the pulse width control voltage and a fixed bias that yields a pulse signal that has no DC component. As the pulse width is varied, the pulse width control voltage raises and lowers the signal keeping its average DC level at zero volts. Pin 1 of the CMOS switch gets a combination of the pulse, the pulse width control voltage, a fixed bias and the sawtooth. This produces a mix that is indistinguishable from two sawteeth. If you can't visualize this, set the Wave Shape parameter (No. 33) to 0 and look at the output of Z10 while varying the Width parameter (No. 34). This signal is also DC free. The A oscillator differs from the B in that its output signal can be replaced with a ring modulator signal when the RING MOD line from the data latch is low. The four NAND gates perform a digital exclusive-or function on the pulse signals from the two oscillators. This produces a perfect ring mod signal if the inputs are square waves, and a reasonable ring mod effect if the inputs aren't square. Z10 buffers whatever wave shapes are selected. Note: the signals at the inputs to the CMOS switches disappear when you select them, because they are connected through the switch to the summing junction of Z10. In other words, the CMOS switches are used as current switches.

4. Filters

The filters are implemented using Doug Curtis' dual state-variable filter chips. A complete analysis of these chips will not be attempted here, but this is basically what occurs in the circuit. Z11 is a CMOS switch, common to both filters, that determines, under control of the Patch parameter, what signals feed the filters. These switches operate in the current mode, as they feed the signal into a 10 ohm resistor R57 (or R58). Thus the signal that appears on pin 3 (or 13) of the CMOS switch is very small, typically 50mV p-p. The filter chip requires signals that small to avoid distortion. The output amplifier, which brings the signal level back up to normal, consists of op-amp Z14 and associated resistors. This circuit provides differential gain, and blocking capacitor C13 (or C14) assures that the offset voltages in the filter chip are not amplified as well. The filter is basically connected as a high-pass filter, where the signal is applied to the lower end of C9 (or C10) and taken off the upper end of the same capacitor. The filter chip, in this case, looks like a shunt inductance and resistance to ground. If CMOS switch Z12B (or Z12C) is switched to ground, this is all the circuit does, and the output buffer provides single ended gain. If the switch is switched the other way, the input signal is delivered to the IN 2 pin on the chip, which is a band-pass input, and to the inverting input of the output buffer. The OUT 1 line thus produces a combination of a band-pass and high-pass response which, when combined out of phase with the input signal, yields a low-pass response. Remember, low-pass + band-pass + high-pass = everything. This configuration was chosen because it has few parts, and because it can perform switching between the low-pass and high-pass function without generating a DC transient.

The three feedback resistors, R69, 71, and 73 (or R70, 72 and 74) provide a tiny amount of positive feedback around the filter that, when the resonance is raised far enough, cause the filter to oscillate. The parallel NPN/PNP transistors counter this effect with negative feedback when the output signal reaches about +3V. This prevents the filter from hard clipping at high resonance levels, providing instead a soft "rounded" distortion.

The F terminals on the filter chip are the inputs to the on-chip expo converters that control the tuning of the filter. Like the oscillator expo converters, these provide negative control. Resistors R5 and R45 (or R6 and R46) scale these inputs at slightly under 0.5V/octave, just like the oscillator. The Q terminals provide negative exponential control of the resonance of the filters. The three resonance control bits from the data latch for each channel are used to encode the setting of the Resonance parameter. When the parameter is 0, the three bits are all logic 1 (5 volts), and when the parameter is 7, the three bits are all at zero. Resistors R47, 49 and 51 (or R48, 50 and 52) combine these in a binary weighted manner. The purpose of the transistor is to provide a resonance boost when the parameter is set to 7. Normally (that is, when the filter isn't being used as an oscillator) at least one of the resonance control bits is high. This turns the transistor on hard, so that the current that flows into the 100 ohm summing resistor R53 (or R54) is thus equal to the sum of the control currents fed into the base of the transistor and the current through the 33k resistor on the collector. As the resonance parameter is increased, less current flows through the base, but the transistor remains saturated. When the resonance parameter makes the final transition from 6 to 7 and all three bits go low, the transistor shuts off and the current through the emitter drops sharply to zero, causing a large increase in Q. This guarantees that all filters will oscillate when set to 7, but not when set to 6. The added 33k resistor (R115 or R116) causes the resonance to be increased slightly at higher frequencies, to overcome a slight reluctance to oscillate.

Op-amp Z29A isn't really part of the filter at all, and should have been drawn someplace else. It's a current inverter. Op-amp Z29B is connected in the rather unconventional "left-facing ground buffer" configuration. Unfortunately, the theory behind this circuit is beyond the scope of this document. Suffice to say that it works perfectly.

See discussion of the previous paragraph in Found in the Service Manual, September 2011.

5. Amplifiers

CMOS switch Z15 (common to both amplifiers) selects a signal to be controlled and feeds it, as a current, into the low impedance (summing junction) input of the VCA chip Z16. The output of this chip is also a current (The output stage of the chip is similar to that of a 3080 OTA chip). The control voltage from the VOLUME A (or B) sample and hold is attenuated to the required 0 to 3V level and applied to the chip's linear control input. The 0.1uF capacitor on this input slows the control voltage changes down just enough to make a sharp attack or release sound like a soft pop and not a sharp tick. The A amplifier's output current is routed to one of the four summing busses in the Channel Mother Board by Z17. The B amplifier's output current is routed to one of three places. If the Patch parameter selects filter FM, this signal current is fed into the frequency control input of the A filter. If the Patch parameter selects the series or parallel filter configuration without filter FM, the signal current is fed back and mixed with the A oscillator. Otherwise, the signal current is mixed into the output. The rest of the signal routing on board is tedious but simple and is easily traced with the help of the Patch parameter diagrams in the Chroma Programming Manual.

Channel Mother Board Circuit Description

The Channel Mother Board consists of the following circuits, as outlined on the schematic:

  1. Sample and hold decoder
  2. Data latch
  3. Data strobe decoder
  4. Oscillator and output mute latch
  5. Noise generator
  6. Output summing amps
  7. Zero crossing detector

Each section will be covered individually in the following descriptions.

1. Sample and hold decoder

This circuit is used to selectively enable one of the 64 sample and hold circuits on the channel boards. Z1 and Z2 form an 8-bit latch that can be written to by the main computer using strobe WR SHA. The low order six bits address the sample and hold, bit 6 is an active low enable signal, and bit 7 is the active low "fast" signal described in the Dual Channel Board Circuit Description. The upper half of the sample and hold address (from data bus bits B3, B4 and B5) are decoded by Z7A, Z7B and Z8. These three bits appear on Z2-2, Z1-10 and Z1-7, and the last bit also appears complemented on Z1-6. The two OR gates and the two one-of-four decoders function as a one-of-eight decoder, enabled by Z1-15. The three low-order bits of the sample and hold address (from Z2-10, -7 and-15) are decoded on the channel boards themselves.

The firmware always manipulates the sample and hold latch in the same three steps. First, it turns off the current sample and hold by writing the sample and hold number to this port with bit 6 (the enable bit) inactive (high). Second, it selects the next sample and hold by writing the new sample and hold number to this port with bit 6 still high. The "fast" bit, bit 7, will be set as necessary and the DAC output voltage will be changed at this time. Third, the sample and hold is enabled by repeating the last operation with bit 6 low. This entire sequence takes approximately 10us and eliminates any possible glitches that might disturb other sample and holds.

Each sample and hold is left selected for at least 100us while the computer does other work. Thus, the enable bit, Z1-15 will be active (low) most of the time. Each of the sample and hold address bits will look remotely like a square wave, as each sample and hold is addressed in a sequence, from 0 to 63. This sequence is disturbed every time a new note is struck.

2. Data latch

The main computer sends digital control signals to each board in a two-step process. First, a 6-bit word is written to the data latch using strobe WR SYND. Second, the data strobe decoder (explained below) is used to transfer the data to the desired latch on any of the channel boards.

3. Data strobe decoder

Once a word is set up in the data latch, it can be copied into any of the latches on the individual channel boards by writing the number of the latch using the WR SYNA strobe. Each channel board has three latches, and therefore has three strobes for triggering them. A fourth strobe to each board is provided for future expansion. Thus, there are 32 total strobes that must be individually controllable by the main computer. Latch Z5 and the right half of flip-flop Z4 form a 5-bit latch to which can be written a five bit address code. The left side of flip-flop Z4 is configured as a crude one-shot by connecting its output through a lag network back into its reset input. Whenever one of the channel board latches is to be strobed, the WR SYNA strobe (which is an active low pulse) will trigger this one-shot on its trailing (rising) edge. Z7C, Z7D and Z9 form a one-of-eight decoder that routes this one-shot pulse according to the lowest 3 bits in the latch number. (These 3 bits come from data bus bits B0, B1 and B2, and appear to Z5-15, Z5-2 and Z4-1, and the last bit also appears inverted on Z4-2.) Each of the eight lines coming out of decoder Z9 corresponds to one of the dual channel boards. The strobe pulse is further routed to one of the four strobe lines on the selected channel board by one of the one-of-four decoders Z10A through Z13B. (The bits that select which of the four strobes to activate are the upper two bits in the latch number. These bits come from data bus bits B3 and B4 and appear on Z5-10 and Z5-7.)

4. Oscillator and output mute latch

Whenever the main computer does a write operation using the WR MSCO strobe, the upper six bits of the data bus are latched on the I/O board and the lower two bits of the data bus are latched by Z6 on this board. All the bits on this "port" are miscellaneous in nature. The two that appear here are mute bits. The low order bit, which appears on Z6 pin 13 (and inverted on Z6 pin 12) is used as an output mute. The next bit, which appears on Z6 pin 1, is used as an oscillator mute bit. It disables the audio input to each filter on the Dual Channel Boards.

5. Noise generator

Two digital noise generator chips, Z14 and Z15, are employed in this circuit. Each chip has its own on-chip clock and a shift-register type noise generator that generates a pseudo-random sequence of 0s and 1s at 12 volt logic levels. Since the two chips run asynchronously, the pseudo-randomness is turned into something truly random and free of repetition. By itself, a random stream of bits sounds like white noise. This signal is buffered and attenuated and delivered to J5 pin 6 on each Dual Channel Board. The noise generator output is also filtered by a network that approximates a 3db per octave rolloff, yielding pink noise. This signal is buffered and delivered to J5 pin 8 on each Dual Channel Board.

6. Output summing amps

The signal currents from each of the Dual Channel Boards are mixed using four summing busses, SUM 0 through SUM 3. CMOS switches Z16 and Z17 route these currents into summing amps Z18 and Z19, or divert them, under control of the output mute bit. The voltage outputs are roughly line level signals, and are sent to the EQ Board.

7. Zero crossing detector

When the outputs are muted, as during auto-tune, the signal current from SUM 0 summing bus is fed into comparator Z20. This comparator "squares up" the signal and feeds it to the I/O Board for measurement. During filter tuning, the signal being processed is a sine wave, and so some positive feedback is utilized (through R11) to keep the comparator from oscillating as the signal slowly passes through zero. The two diodes clamp the input to the comparator. The negative clamp uses a germanium diode for its lower forward drop. The intent here is to protect Z16 pin 4 from excessive voltages.

Power Supply

The power supply consists of the following circuits:

  1. Primary and transformer
  2. Analog 5V regulator
  3. Analog 12V regulator
  4. Analog -12V regulator
  5. Digital 5V regulator
  6. Digital 5V preregulator
  7. Reset circuit

Each will be covered individually in the following descriptions.

1. Primary and transformer

The power transformer in the Chroma is a dual primary design. The DPDT line voltage selection switch S1 is used to connect the two identical primaries in parallel for operation at 120VAC, or in series for operation at 220VAC. R1 and R2 are metal-oxide varistors which act as a low impedance clamp at voltages above those expected from the power line. This prevents high voltage transients from entering the unit. The rear panel power connector includes an RFI filter to further isolate the inside and outside of the instrument from each other.

The transformer has only one secondary winding with a grounded center tap. All voltages in the system ultimately come from one of three full-wave rectifiers connected to this winding. CR1 and 2 (the large rectifiers on the board) provide power to the digital preregulator and regulator. CR6 and 7 provide power to the positive analog regulators. CR8 and 9 power the negative analog regulator.

2. Analog 5V regulator

This regulator takes its input from filter capacitor C7, which has somewhere between 16 and 33 volts on it, and generates a very stable, but not particularly powerful, 5 volt reference. Op-amp Z1A and transistor Q6 make up the active part of the regulator. Resistor R19 sets the current limit at roughly 250mA. Z3, though it behaves like a zener diode, is actually an IC reference that has a very low dynamic impedance and temperature coefficient. It establishes pin 2 of the op-amp at 1.2 volts below the output voltage of the circuit. R17 and R20 control the gain of the circuit, and R21 and trimmer R22 allow the output to be set at exactly 5.000V. R42 is only there to make sure that the circuit starts up correctly.

3. Analog 12V regulator

Taking its input from the same filter capacitor, this circuit amplifies the 5V reference and produces 12V at up to about 700mA. Op-amp Z2A and transistor Q7 make up the active part of the regulator. R23 and R24 set the gain at 12/5, and Q8, R25 and R26 provide current limiting.

4. Analog -12V regulator

This circuit takes its input from filter capacitor C11 and its reference from the output of the 12V regulator. Op-amp Z28 is connected as a unity gain inverting amplifier (R27 and R28 set the gain). Its output, which can only go as low as ground, drives cascode transistor Q11, which in turn drives pass transistor Q9. The current limiting circuit is slightly "upside-down" due to the fact that the pass transistor inverts. R31 sets the limit at about 700mA, and when this is exceeded current is diverted from the input of the cascode transistor. Diode CR13 is only there to protect the input of the op-amp from negative voltages.

5. Digital 5V regulator

This circuit, based around op-amp Z1B and power MOSFET Q4, acts as a voltage follower, boosting the available current to several amps. A MOSFET was chosen because of its high input impedance and its ability to operate with only a few tenths of a volt across it. At high currents, the resistor in a conventional current limiting circuit begins to dissipate appreciable current because it can have up to 0.7V across it. This circuit uses differential sensing to reduce the voltage across sense resistor R12. The 12k and 120 ohm resistors (R13 and R15) are driven with 5V between them, while the 910 ohm and 6.8 ohm resistors (R11 and R14) see between them whatever the current sensing voltage is. This extra bias means that the current sense resistor only need have about a quarter of a volt across it to start current limiting. The difference in ratio between R13/R11 and R15/R14 results in a foldback limiting characteristic as well.

6. Digital 5V preregulator

The 5V regulator takes its input from the large filter capacitor C3. To keep the dissipation in the regulator down, this voltage is preregulated to about 6V. In fact, there is a crowbar-type overvoltage protector (Z4) mounted right across the filter capacitor terminals that makes sure this voltage doesn't get much higher than 7V. The preregulator takes its input from the secondary through CR1 and CR2, but no filtering is performed prior to the preregulator. Instead, the preregulator functions as a switch that turns on and off at the 120Hz rectified line voltage rate.

The switch consists of power transistor Q1 (the TO-3 package) driven by power MOSFET Q2. This combination was chosen because of its low on voltage (not much more than a volt) at high currents (20A pulses are found in this circuit). The gate of the MOSFET is normally pulled up to the unregulated plus supply voltage by R6 (through R4), meaning that the switch is normally on. As the power line voltage rises during any particular half-cycle, a point is reached where the switch becomes forward biased. At this point, filter capacitor C3 starts to charge. If you look at the junction of CR1 and CR2 with a scope, you should see the voltage rising to about 7V and then leveling off when hit with the heavy load of the filter capacitor. As soon as the filter capacitor is charged sufficiently to run the 5V regulator, the switch is turned off. This appears as the sudden rise in the rectifier output voltage. Thus, the rectifier output looks like a conventional full-wave rectified sine wave with a triangular "bite" taken out of it during its rise by the temporary connection to the large filter capacitor. When the switch turns off, the transformer secondary voltage continues on up in voltage to where it charges the analog supply filter capacitors, C7 and C11.

The rest of the preregulator circuit is involved with determining when in each cycle to turn off the switch. Transistor Q3 senses (through R3 and R7) when the rectifier voltage gets a few volts above the final output voltage. When it does, it starts to turn off the switch circuit. The sudden removal of the load causes the voltage being sensed to rise sharply. Thus there is positive feedback on the circuit, assuring that the switching will occur quickly. The emitter of the sense transistor Q3 is connected to the top of the current sensing resistor R12 and not to the output in order to allow for its voltage drop. Resistor R7 is connected to the bottom of the current sense resistor, causing the drop across the resistor to be overcompensated for, which allows for the resistance of, and voltage drop in, pass transistor Q4 at higher output currents. The trimmer R46 allows the trip point of this circuit to be adjusted.

Note that the preregulator is referenced to the digital 5V output, and not to some absolute reference. Under normal operation, the preregulator will be putting out about 6VDC, with .5 volts of ripple, and the regulator will be cutting that down to a smooth 5V. If the output is shorted, the preregulator voltage will automatically come down to about 1V, maintaining a constant drop across pass transistor Q4. This keeps the power dissipation down under short-circuit conditions.

7. Reset circuit

In any computer system, there is a need for a system RESET signal that remains active until the power supply is fully stabilized and the processor clock has run for a bit. This is usually attained with a simple RC network. But in a computer system that employs non-volatile RAM, the RESET signal must also be asserted again before the supply drops out of regulation when the power is shut off. If this requirement isn't met, the computer can produce spurious signals when the supply falls below 4.75V, damaging the integrity of its own memory. In order to sense power failure "before it happens," it is necessary to create a filtered version of the rectified line voltage that has a faster "droop" than that of the main filter capacitor, C3. Capacitor C10 performs this function. C10 takes its charge from the same rectifiers as the analog positive supplies, but is isolated from filter capacitor C7 by the extra diode, CR10. C10 is pulled down, not to ground, but toward the opposite supply by R40 (CR16 prevents this voltage from ever actually going negative). Thus, the voltage on C10 will be a crude, rounded, sawtooth at 120Hz, that charges up to 25V or so and then droops sharply. R39 and C12 form a low-pass filter, or would if it weren't for CR15. During power up, C10 shows its characteristic sawtooth, and C12 shows a gradual rise in voltage towards the DC level of the sawtooth. CR15 keeps this voltage from getting any higher than the negative-most extreme of the sawtooth. During power-down, the sawtooth stops abruptly and CR15 quickly pulls the voltage on C12 back to ground, before the supply has a chance to come out of regulation.

R38 couples this signal into the Schmitt trigger circuit consisting of Q12 and Q13. This circuit "squares up" the very slow rise of C12's voltage during power-up, and its rather slow fall during power-down. Note the positive feedback loop in this circuit. The voltage on C12 has to rise to about 5V before the circuit switches on. Then, the voltage on C12 has to drop to about 4V before it switches off again. Zener diode CR14 opens up the loop and forces RESET active if the digital 5V supply (which powers this circuit) falls out of regulation.

EQ Board

The EQ Board consists of the following circuits, as outlined on the schematic:

  1. Volume and ground isolation
  2. Custom equalization
  3. Audio mixer and mute
  4. Tone controls
  5. Balanced output amplifiers

Each will be covered individually in the following descriptions.

1. Volume and ground isolation

This circuit controls the volume of the signals from the quad outputs of the Channel Mother Board. The VCA chips that are used are the same as those used in the channels themselves. The input terminals look like summing junctions and are thus fed through resistors. The outputs are currents that are converted to voltages by op-amps Z3 and Z4. Note that the VCA chips are the only circuits on the board that are referenced to the normal ground line from the power supply. Though not shown on the schematic, this line actually comes from the Channel Mother Board along with the quad audio signals. All the remaining circuits are referenced to the OUTPUT GND line which comes directly from the rear panel. If any differential voltage exists between these two grounds, it will not affect the signal, as the signal is passed in the form of a current from the high output impedance of the VCAs to the low input impedance of the op-amps.

The control voltage inputs on the VCA chips are all tied in parallel and driven by the VOLUME potentiometer R5. The control voltage inputs have a linear transfer function and expect voltages from 0 to about 2 volts. R6 and R7 divide the slider voltage down to this level, and incidentally make the apparent taper of the volume control a little more "audio" by loading down the slider when it is set near middle.

Note that the cassette audio signal is mixed in with the 0 channel. This allows easy cueing of tapes by ear, without having to unplug the earphone jack on the cassette recorder. Note also that the VCAs are powered from a heavily filtered 4.3V supply shown on the right side of the schematic. It is derived fro the analog +5V reference to the TUNE slider, and is intended to reduce noise coupled into the VCAs.

2. Custom equalization

No circuits are actually installed for this function, but there are solder pads on the board for possible installation of fixed equalization modules in channels 1, 2 and 3. The quad outputs are wired up to stereo phone jacks that function as combination send/receive jacks. The tip of each jack is driven with the (unequalized) output signal. The ring can be used as an input to the final mono mix. If a plug is not inserted into the jack, the ring is driven (via the ring shunt) with the equalized output signal. Thus, using a jack as a send/receive connector causes any internal custom EQ to be bypassed. If the jack is left empty, the custom EQ for that channel remains in the circuit, and may be selected using the Output Select parameter.

3. Audio mixer and mute

The quad outputs (or the signals fed in on the rings of the four output jacks) are mixed in this circuit. JFET Q1 and CR1 form an analog switch that interrupts the signal during system RESET (power-up and power-down). R25 and R26 level shift the RESET signal, as the JFET expects a negative control voltage. C17 is necessary to filter any computer noise from this line.

4. Tone controls

This is an ordinary three-band tone control circuit. C10 and C11 "short out" the BASS control at high frequencies, allowing it to affect the response only at low frequencies. C15 "disconnects" the TREBLE control from the op-amp at low frequencies, allowing it to affect the response only at high frequencies. The MIDDLE control uses a combination of the two effects.

5. Balanced outputs

These two circuits are simple power amplifiers using op-amps Z6A and Z6B as voltage followers. Increased current output capability is provided by the NPN/PNP output stage added inside each feedback loop. The diodes and 22 ohm resistors make the transistors operate class AB.

Stack Switch Boards

The Right Stack Switch Board contains the following circuits, as outlined on the schematic:

  1. Bank select decoder
  2. Switch banks
  3. Sense amps

The Left Stack Switch Board is an extension of the Right Stack Switch Board and has the same circuits minus the sense amps. These circuits will be covered individually in the following descriptions. The term "stack switch" comes from the way each switch is assembled as a stack of different layers.

Bank select decoder

When the keyboard scanning computer on the I/O Board wants to read the state of a bank of eight keyswitches, it addresses the bank by putting one of 16 binary numbers on the kA lines. These lines drive the bank select decoders (Z1) on each board (KA2 is inverted on the right board), causing exactly one of the 16 decoder outputs to be activated. These outputs are open-collectors, and, when activated, connect a row of eight switch contacts to ground.

Switch banks

Each keyswitch has a lower, normally closed, contact called the A contact, an upper, normally open, contact called the B contact, and a center wiper contact that is moved by the key. The keyboard has 64 keys which are grouped into eight banks of eight keys each. Half of these banks are handled by each Stack Switch Board. The keyboard scanning computer reads the state of a bank of A contacts or a bank of B contacts by connecting the row of contacts to ground. All the wiper contacts connect, through resistor packs, to the keyboard bus KB0 through KB7. This is a current summing bus, and any closed contacts in the selected bank will cause 500uA to be sinked from the appropriate line on the bus.

Sense amps

The keyboard bus is pulled up to the +5V rail by the 100 ohm resistors in Z6. A closed contact in the selected switch bank will pull 500uA from a bus line, which will pull it, and one of the comparator (Z7 and Z8) inputs, down 50mV. The other inputs on the eight comparators are connected to a constant voltage that is about 25mV below the +5V rail. Thus, each comparator resolves the state of one switch in the selected bank and produces a standard 5V logic level on one of the keyboard data lines KD0 through KD7. Each data line that goes back to the keyboard scanning computer will be a 0 if the corresponding switch contact is open or a 1 if it is closed.

The sense amps are powered from the +12V supply.