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Section 0

Service Manual: System Overview

Chroma synthesizers are an extraordinary achievement of America's research and engineering sciences. The Chroma is a sixteen channel fully programmable polyphonic synthesizer with fifty preset sounds complete with touch responsive keyboard.

The Chroma is computer-based using two microprocessors, one for keyboard dynamics, the other for high-speed digital control of the analog channels.

In its most basic form, the Chroma consists of a computer (in the digital domain), synthesizer channels (in the analog domain) and input/output support hardware (interfacing between the digital and analog domains) as illustrated in Figure 1-1.

Fig. 1-1 Basic System

The computer consists of a central processing unit (CPU) and memory. The CPU is a 68B09 microprocessor clocked at 8MHz. Memory consists of 7K random access memory and 16K read only memory. RAM is divided into 4K NMOS for data structuring (read/write memory) and 3K CMOS non-volatile for storage of the fifty sounds. The 16K ROM contains the control program for the system using eight 2K EPROMs. The system is memory mapped and as shown in Figure 1-2 even the I/O read/write operations appear as memory locations to the 68B09.

Eight Dual Channel Boards make up the sixteen synthesizer channels. Each board contains two voltage controlled oscillators, two voltage controller filters, two voltage controlled amplifiers, selectable waveforms and CMOS switching for versatile patching between circuits. These are supplemented with four envelope generators, two sweep generators (each capable of sixteen sweep waveforms from sine wave to random) and two glides per board. The envelopes, sweeps and glides are software generated, no hardware circuits exist for these functions. Figure 1-3 illustrates the basic architecture of a Dual Channel Board.

Fig. 1-2 Chroma Memory Mapped System

Fig. 1-3 Dual Channel Board Basic Architecture

The interconnections between the blocks shown in Figure 1-3 are a function of the preset sound selected or the sound programmed by the user. For example: Sweep "B" might go to Oscillator "A," Oscillator "A" to Filter "A," Filter "A" to Filter "B," Filter "B" to Amplifier "A," while Envelope "1B" might go to Filter "A" with Envelope "2A" going to Filter "B," etc. I think you get the idea. The patching is extremely versatile, the synthesizer very powerful. Remember, eight Dual Channel Boards result in thirty-two envelopes, and sixteen sweeps, oscillators, filters and amplifiers. The channel boards are divided into two sections, "A" and "B." The "A" section is controlled by "A" parameters and and "B" section by "B" parameters called up from the front panel individually or together.

Fig. 1-4 System Interfacing

The I/O or input/output chiefly consists of a keyboard scanning computer, a timer for cassette and auto-tune measurements and system timing, various decoders/drivers and two important converter circuits. The ADC or "A" to "D" converter looks at analog levels such as a slider or volume pedal and converts it to digital computer data. The DACs or "D" to "A" converters change digital converter data to analog voltages to operate the VCOs, VCFs and VCAs on the Dual Channel Boards. Figure 1-4 illustrates this hand-shaking.

A system block diagram is shown in Figure 1-5. When a keyboard switch is depressed the keyboard scanning computer (Intel 8039) generates the note number and velocity then interrupts the CPU (Motorola 68B09). The CPU responds by fetching a vector address from EPROM memory which puts it into a sub-routine to read the note number then the velocity from the 8-bit bi-directional bus. The CPU manipulates this data using NMOS RAM under control of the EPROM firmware and writes digital data to the DACs for conversion to analog voltages. A serial stream of 64 discrete varying voltages from the DAC circuitry is continually sampled to provide oscillator pitch, pulse width, filter cutoff and volume. Other data structured by the CPU (influenced by the program selected from CMOS RAM) is written to the strobe decoder to establish the correct patches or interconnections on the Dual Channel Boards.

Control changes such as volume pedal, levers or sliders are read from the ADC by the CPU, manipulated in NMOS RAM, and subsequently change the sound. Changes in program selected or editing from the panel switch array, will also alter the data in NMOS RAM. This will affect the sound and change the display. The audio out from the Dual Channel Board is folded back during auto-tune operations to a zero crossing detector. The period of the output square wave is timed and read by the CPU. Pitch corrections are then written to the DACs for proper volts per octave and offset by the CPU. During auto-tune the CPU measures each of the sixteen oscillators twice, six octaves apart to establish correct volts per octave then a third time to adjust any offset. The filters are patched into self-resonance and also tuned during autotune. The entire auto-tune cycle takes about five seconds and should be done one or two times within an hour by the user. The timer also provides the CPU with cassette times for differentiating between the 1200Hz and 600Hz tones used to represent data bit levels on tape. Additionally, the timer helps regulate the main software loop.

Not shown on the system block diagram are the cassette interface, the audio EQ chain or the external computer interface. The external computer interface is a parallel port extending the 8-bit bi-directional bus complete with 8-bit input and output buffering. An expander module (with 8 more dual channels) may be connected to this port or an external computer may be connected for sequencing, multi-tracking, etc., or both expander and computer may be connected at the same time.

You can see from the previous description that the computer (68B09) is central to everything else in the system. Figure 1-6 illustrates the structure of the overall system.

An in-depth description of all Chroma circuits is detailed in Section 2 (Circuit Descriptions).

Fig. 1-5 System Block Diagram

Fig. 1-6 System Structure